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MM74HC00FAIN/a5avaiQuad 2-Input NAND Gate
MM74HC00NSN/a130avaiQuad 2-Input NAND Gate


MM74HC00 ,Quad 2-Input NAND GateFeaturesLS-TTL gates with the low power consumption of standardCMOS integrated circuits. All gates ..
MM74HC00M ,Quad 2-Input NAND GateMM74HC00 Quad 2-Input NAND GateSeptember 1983Revised January 2005MM74HC00Quad 2-Input NAND Gate
MM74HC00MTC ,Quad 2-Input NAND GateElectrical Characteristics V = 5V, T = 25°C, C = 15 pF, t = t = 6 nsCC A L r f GuaranteedSymbol Par ..
MM74HC00MTCX ,Quad 2-Input NAND GateMM74HC00 Quad 2-Input NAND GateSeptember 1983Revised January 2005MM74HC00Quad 2-Input NAND Gate
MM74HC00MX ,Quad 2-Input NAND GateFeaturesThe MM74HC00 NAND gates utilize advanced silicon-gate

MM74HC00
Quad 2-Input NAND Gate
MM74HC00 Quad 2-Input NAND Gate September 1983 Revised February 1999 MM74HC00 Quad 2-Input NAND Gate static discharge by internal diode clamps to V and CC General Description ground. The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to Features LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs. � Typical propagation delay: 8 ns All devices have high noise immunity and the ability to � Wide power supply range: 2–6V drive 10 LS-TTL loads. The 74HC logic family is function- � Low quiescent current: 20 μA maximum (74HC Series) ally as well as pin-out compatible with the standard 74LS � Low input current: 1 μA maximum logic family. All inputs are protected from damage due to � Fanout of 10 LS-TTL loads Ordering Code: Order Number Package Number Package Description MM74HC00M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74HC00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC00N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Logic Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View © 1999 DS005292.prf
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