MM74C76N ,Dual J-K Flip-Flops with Clear and PresetApplicationsClear or preset is independent of the clock and is accom-• Automotiveplished by a low l ..
MM74C85N ,4-Bit Magnitude ComparatorFeaturesThe MM74C85 is a four-bit magnitude comparator which
MM74C76N
Dual J-K Flip-Flops with Clear and Preset
MM74C73 • MM74C76 Dual J-K Flip-Flops with Clear and Preset October 1987 Revised January 1999 MM74C73 • MM74C76 Dual J-K Flip-Flops with Clear and Preset General Description Features The MM74C73 and MM74C76 dual J-K flip-flops are mono- � Supply voltage range: 3V to 15V lithic complementary MOS (CMOS) integrated circuits con- � Tenth power TTL compatible: Drive 2 LPTTL loads structed with N- and P-channel enhancement transistors. � High noise immunity: 0.45 V (typ.) CC Each flip-flop has independent J, K, clock and clear inputs � Low power: 50 nW (typ.) and Q and Q outputs. The MM74C76 flip flops also include preset inputs and are supplied in 16 pin packages. This � Medium speed operation: 10 MHz (typ.) flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Applications Clear or preset is independent of the clock and is accom- • Automotive plished by a low level on the respective input. • Data terminals • Instrumentation • Medical electronics • Alarm systems • Industrial electronics • Remote metering • Computers Ordering Code: Order Number Package Number Package Description MM74C73N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide MM74C76M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74C76N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagrams MM74C73 MM74C76 Note: A logic “0” on clear sets Q to a logic “0”. Note: A logic “0” on preset sets Q to a logic “1”. Note: A logic “0” on clear sets Q to logic “0”. Top View Top View © 1999 DS005884.prf
