MM74C74N ,Dual D Flip-FlopFeaturesThe MM74C74 dual D-type flip-flop is a monolithic comple-
MM74C74M-MM74C74N
Dual D Flip-Flop
MM74C74 Dual D-Type Flip-Flop October 1987 Revised May 2002 MM74C74 Dual D-Type Flip-Flop General Description Features The MM74C74 dual D-type flip-flop is a monolithic comple-Supply voltage range: 3V to 15V mentary MOS (CMOS) integrated circuit constructed with 2 Tenth power TTL compatible: Drive 2 LPT L loads N- and P-channel enhancement transistors. Each flip-flop High noise immunity: 0.45 V (typ.) CC has independent data, preset, clear and clock inputs and Q and Q outputs. The logic level present at the data input isLow power: 50 nW (typ.) transferred to the output during the positive going transition Medium speed operation: 10 MHz (typ.) with 10V of the clock pulse. Preset or clear is independent of the supply clock and accomplished by a low level at the preset or clear input. Applications • Automotive Data terminals Instrumentation Medical electronics Alarm system Industrial electronics Remote metering Computers Ordering Code: Order Number Package Number Package Description MM74C74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MM74C74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Truth Table Preset Clear Q Q n n 0000 0110 1001 11 Q Q n n (Note 1) (Note 1) Note 1: No change in output from previous state. Note: A logic “0” on clear sets Q to logic “0”. A logic “0” on preset sets Q to logic “1”. Top View © 2002 DS005885
