MM74C373N ,3-STATE Octal D-Type LatchMM74C373 • MM74C374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-FlopOctober 1987Revised ..
MM74C374N ,3-STATE Octal D-Type Flip-FlopsMM74C373 • MM74C374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-FlopOctober 1987Revised ..
MM74C42N ,BCD-to-Decimal DecoderMM74C42 BCD-to-Decimal DecoderOctober 1987Revised May 2002MM74C42BCD-to-Decimal Decoder
MM74C42N. ,BCD-to-Decimal DecoderFeaturesThe MM74C42 one-of-ten decoder is a monolithic comple-
MM74C373N-MM74C374N
3-STATE Octal D-Type Latch
MM74C373 • MM74C374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop October 1987 Revised January 2004 MM74C373 MM74C374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description Features The MM74C373 and MM74C374 are integrated, comple-Wide supply voltage range: 3V to 15V mentary MOS (CMOS), 8-bit storage elements with 3-High noise immunity: 0.45 V (typ.) CC STATE outputs. These outputs have been specially Low power consumption designed to drive high capacitive loads, such as one might TTL compatibility: find when driving a bus, and to have a fan out of 1 when driving standard TTL. When a high logic level is applied to Fan out of 1driving standard TTL the OUTPUT DISABLE input, all outputs go to a high Bus driving capability impedance state, regardless of what signals are present at 3-STATE outputs the other inputs and the state of the storage elements. Eight storage elements in one package The MM74C373 is an 8-bit latch. When LATCH ENABLE is Single CLOCK/LATCH ENABLE and OUTPUT DIS- high, the Q outputs will follow the D inputs. When LATCH ABLE control inputs ENABLE goes low, data at the D inputs, which meets the set-up and hold time requirements, will be retained at the20-pin dual-in-line package with 0.300” centers takes outputs until LATCH ENABLE returns high again. half the board space of a 24-pin package The MM74C374 is an 8-bit, D-type, positive-edge triggered flip-flop. Data at the D inputs, meeting the set-up and hold time requirements, is transferred to the Q outputs on posi- tive-going transitions of the CLOCK input. Both the MM74C373 and the MM74C374 are being assem- bled in 20-pin dual-in-line packages with 0.300” pin cen- ters. Ordering Code: Order Number Package Number Package Description MM74C373M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide (Note 1) MM74C373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74C374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2004 DS005906
