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MM54C32J
Quad 2-Input OR Gate
TL/F/5881
MM54C32/MM74C32
Quad
2-Input
Gate
February 1988
MM54C32/MM74C32 Quad 2-Input OR Gate
General Description
Employing complementary MOS (CMOS) transistorsto
achievelow powerand high noise margin, these gatespro-
vide thebasicfunctionsusedinthe implementationof digital
integrated circuit systems.TheN-and P-channel enhance-
ment mode transistors providea symmetrical circuit with
output swings essentially equaltothe supply voltage. This
resultsin high noise immunity overa wide supply voltage
range.NoDC power other thanthat causedby leakagecur-
rentis consumedduring static conditions. Allinputsarepro-
tected against static discharge damage.
Features Wide supply voltage range 3.0Vto 15V Guaranteed noise margin 1.0V High noise immunity 0.45V VCC (typ.) Low power fanoutof2
TTL compatibility driving74L
Connection Diagram
Dual-In-Line Package
TL/F/5881–1
Top View
OrderNumber MM54C32orMM74C32
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
