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MM5368NSN/a20avaiCMOS OSCILLATOR DIVIDER CIRCUIT


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MM5368
CMOS OSCILLATOR DIVIDER CIRCUIT
General Description
The MM5368 is a CMOS integrated circuit generating 50 or
60 Hz, 10 Hz, and 1 Hz outputs from a 32 kHz crystal
(32,768 Hz). For the 60 Hz selected output the input time
base is divided by 546.133, tor the 50 Hz mode it is divided
by 655.36. The 50/60 Hz output is then divided by 5 or 6 to
obtain a 10 Hz output which is further divided to obtain a
1 Hz output. The 50/60 Hz select input can be floated for a
counter reset.
NNutional Semiconductor
MM5368 CMOS Oscillator Divider Cirtuit
Features
a 50/60 Hz output
a 1 Hz output
a 10 Hz output
I: Low power dissipation
a Fully static operation
I: Counter reset
I: 3.5V-15V supply range
I: On-chip oscillator-ttming and Ioad capacitors are the
only required external components besides the crystal.
(For operation below 5V it may be necessary to use an
_ 1 Mn pullup on the oscillator output to insure start-
Block and Connection Diagrams
OS!) 5
DECODE
M/till Hz 7 &
SELECT sum
LOGII:
COUNTER RESET
50/60 Hz
00TPOT
10 Hz '
OUTPUT
OUTPUT
(twoo') TL/F/6133-1
FIGURE t
Dual-ln-Line Package
50160 Hz our-', U 2-im,
vss " 2- 50/60 Hz sum _
Order Number MM5368N
a a See NS Package Number Nan
Ill Hz 00TPllT-% - as: m
1ilr00TPllT- "u-0$il INT
TLtF/6133-2
Top Vlew
FIGURE 2
© 5501.112“ McielahS EH]. ©
8989“!”
Absolute Maximum Ratings
" Mllltary/Aerospace specified devices are required, Maximum V00 Voltage 16V
please contact the National Semiconductor Sales Operating VDD Range 3.5V 3 Von g 15V
tmltttUDltttrhutors for availability and spetMcatlons L e a d Temperature (Soldering, 10 sec.) 300°C
Voltage at Any Pin -0.3V to VDD + 0.3V
Operating Temperature 0°C to + 70''C
Storage Temperature -65'C to + 15ty'C
Electrical Characteristics TA within operating range, vss = 0V
Parameter Conditions Min Typ Max Units
QuiescentCurrent Drain VDD = 15V; 50/60 Select Floating 10 p.A
Operating Current Drain le = 32 kHz, VDD = 3.5V 60 WA
th = 32 kHz, VDD = 15V 1500 pA
Maximum Input Frequency VDD = 3.5V 64 kHz
VDD = 15V 500 kHz
Output Current Levels VDD = 5V
Logical "r',Soume VOH = Vss + 2.7V -400 pA
Logical “O”, Sink VOL = Vss + 0.4V 400 “A
VDD == 9V
Logieal"1",Source VOH = vss + 6.7V -1500 FA
Logical "o", Sink VOL = vss + 0.4V 1500 p.A
input Current Levets 50/60 Select Input (Note 1)
Logical "l" (IIH) VDD == 3.5V, VIN 2 0.9 VDD f 50 0A
Logical "1" am) VDD = 15V, VlN l 0.9 V00 3 mA
Logical "0" flu) VDD T 3.5V, VIN 2 0.1 VDD 20 WA
Logical "0" (IIL) VDD = 15V, VIN 2 0.1 V00 1 mA
Note It The input current level test is performed by first measuring the open circuit voltage at the 50/60 Hz select pin. It the voltage is "high", make the Im test. It
the voltage is "low", make the ItL test. The state ot the 50/60 Hz select pin may be changed by applying a pulse to OSC IN (pin 6) while the 50/60 Hz pin is open
circuit.
Functional Description (Figure t)
The MM5368 initially divides the input time base by 256.
From the resulting frequency (128 Hz for 32 kHz crystal) 8
clock periods are dropped or eliminated during 60 Hz opera-
tion and 28 clock periods are eliminated during 50 Hz opera-
tion. This frequency is then divided by 2 to obtain a 50 or
60 Hz output. This output is not periodic from cycle to cycle;
however, the waveform repeats itself every second. Straight
divide by 5 or 6 and 10 are used to obtain the 10 Hz output
and the 1 Hz outputs.
The 60 Hz mode is obtained by tying pin 7 to VDD. The
60 Hz output waveform can be seen in Figure 3. The 10 Hz
Timing Diagrams
and 1 Hz outputs have an approximate 50% duty cycle. in
the 50 Hz mode the 50/60 select input is tied to Vss. The
50 Hz output waveform can be seen in Figure a. The 10 Hz
output has an approximate 40% duty cycle and the 1 Hz
output has an approximate 50% duty cycle.
For the 50/60 Hz select input floating, the counter chain is
held reset. except for the initial toggle flip-flop which is
needed for the reset function. A reset may also occur when
the input is switched (Figure 4). To insure the floating state,
current sourced from the input must be limited to 1.0 "A and
current sunk by the input must be limited to 1.0 pLA for
VDD = 3.5V.
OUTPUT L
7.8 tttt--
...______--
[ICLOCK DHDPPED
OUTPUT
PHASE SHIFTED EVERY ll BLOCKS DUE TO
ELIMINATION OF 1 INPUT CC0tKli.tr.,128 H1 CLOCK)
EVERY 5128 Hz CLOCKS
" PHASE sm mu 3 TlMES/SEC
DUE " ELIMINATION OF 3
128 Ht CLOCKS TL/F/6183-3
FIGURE 3. 50/60 Hz Output
Cl iaS011ii!q 00925111: 188 D
'"-=---r-=-=-=-=
Timing Diagrams (Continued)
FLOATING
"mc-r""-""""'"-""").;""- - --.-r.-----.--
Cl, l I
SELEEI
OUTPUT OF IST TOGGLE
FLlP-FLOP
[16 Hill o-l
TL/F/6133-4
RESET LEVEL on
CLDBK nsrscr
50/60 , cmcun
saith"-"
FIGURE 4. 50/60 Select and Reset
Typical Applications
TL/F/6133-5
RESET LATCH
no ll' 5
7 F SS usmat
5 o t 50/50 50/50 l =NVV-
rc,77"a ouyszucr Ht IS I n I
masses 3 lf t
10 He mncsn "-NVv-- - - - "==
. 'AAN- I I l I
as: m Ith F- : ' ' ' o
LU-MN-
'lf the crystal used is a microwatt type an '
R value will be required to limit power to Ilss
the crystal. - 11 10 a ,
3.5V R = 0
5V R ' 100K
10V R = 330K 'IX' = "Ir.'
FIGURE 5. 10 Minute (9:59.9) Tlmer
TL/F/6133-6
Cl ESDLLBH 0092511? tll" E3
8989WW
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