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MM5309NNSN/a3avaiDIGITAL CLOCKS
MM5311NNSN/a1avaiDIGITAL CLOCKS


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MM5309N-MM5311N
DIGITAL CLOCKS
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National
Semiconductor
Digital Clocks
’MM5309, MM5311, MM5312, MM5313,
VMM531 4, 1MM5315 Digital Clocks
General Description T N I
These digital clocks are monolithic MOS '/tegrated
circuits utilizing P-channel 2'v'ltohrielLlteidintg2tgt'
mode and ion implanted. depletion mode devices. The
devices provide all the logic required to build several
types of clocks. Two display modes (4 or 6-digits)
facilitate end-product designs of varied sophistication.
The circuits interface to LED and gas discharge displays
with minimal additional components, and require only
a single power supply. The timekeeping function
operates from either a 50 or 60 Hz input, and the dls-
play format may be either " hours (with leading-zero.
blanking) or 24hnyrs. Outputs consist of multiplexed
display drives (BCD and Tsegment) and digit enables.
The devices operate over a power supply range of 11V
to 19V and do not require a regulated supply. These
clocks are packaged in dual-in-line packages.
Features
I tit) or 60 Hz operation
I tt or 24-hour display format
I 'Leading-zero blanking (12-hour format)
I 7-segrdent outputs
II Single power supply
II Fast and slow set controls
II Internal rhuhiplex oscillator
II For features of individual clocks, see Table I
Applications
l Desk clocks
II Automobile clocks
II lndustrialclocks
II Interval Timers
TABLEI
FEATURES MM5309 MM5311 MM5312 MM5313 MM5314 MM5315
BCD Outputs X X X X X
4/6-Digit Display Mode X X X X X
Hold Count Control X X X X
1 Hz Output _ X X
Output Enable Control X X X
Reset X X
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TOP Vim TOP Vim
Order Number MM5309M I)
See Package 23
Connection Diagrams (Dual-ln-Line Packages)
Order Number MM5311N
See Package 23
SLSSWIN ‘vl-GSWW ‘ELESWEN ‘ZLSSWW ‘H-ESWW ‘MESWW
MM5309, MM53’11, MM531x-2, MM531'3, MM5314, W315,
V . ~1‘u‘m’
'4 1}. -;
Absolute Maximum Ratings
Voltage at Any Pin
Operating Temperature
Storage Temperature
Lead Temperature (Soldering, 10 seconds)
vss + 0.3 to Vss -,20V
-25oC to +70°c
-65°C to +150°c
Electrical Characteristics TA within operating range, Vss = 11V to 19V, VDD = 0V, unless otherwise specified.
PARAMETER CONDITIONS MIN TYP l MAX _ _ UNITS
Power Supply Voltage Vss (VDD = 0V) . 11 19 V
Power Supply Current vss = 14V, (No Output Loads) 10 mA
50/60 Hz Input Frequency dc 50 or 60, 60k Hz
50/60 Hz Input Voltage V
Logical High Level Vss--1 vss vss V
Logical Low Level VDD VDD Vss-10 V
Multiplex Frequency Determiried by External R & C . 0.100 1.0 60 kHz
All Logic Inputs Driven by External Timebase dc 60 kHz _
Logical High Level Internal Depletion Device to Vss Vss-1 vss vss V
Logical Low Level VDD VDD Vss-10 V
555 and 7-Segment Outputs T
Logical High Level Loaded 2 k9. to VDD 2.0 20 mA source
Logical Low Level 0.01 _ mA source
Digital Enable Outputs
Logical High Level 0.3 mA source
Logical Low Level Loaded 100 n to Vss 5.0 25 mA sink
Connection Diagrams (Cont'd) Dual-ln-Line Packages (Top Views)
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Order Number MM5312N /
See Package 22
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Order Number MM5314N
See Package 22
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MULTIPLEXED
Order Number MM5313N
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Order Number MM5315N
See Package 23
Functional Description
A block diagram of the MM5309 digital clock is shown
in Figure r. MM5311, MM5312, MM5313, MM6314
and MM5315 clocks are bonding options of MM5309
clock. Table I shows the pin-outs for these clocks.
50 or 60 H, Input: This input is applied to a Schmitt
Trigger shaping circuit which provide-proximately
5V of hysteresis and allows using a filtered sinewave
input. A simple RC filter such as shown in Fig'u're 10
should be used to remove possible line voltage transients
that could either cause the clock to gain time or damage
the device. The shaper output drives a counter chain
which performs the timekeeping function.
50 or 60 Ha Select Input: This input programs the
prescale counter to divide by'either 50 or 60 to obtain a
1 Hz timebase. The counter is programmed for 60 Hz
operation by connecting this input to Vtth. An internal
depletion device is common to this pin; simply leaving
this input unconnected programs the clock for 50 Hz
operation. As shown in Figure f, the prescale counter
provides both 1 Hz and 10 Hz signals, which can be i
brought out as bonding options.
Time Setting Inputs: Both fast and slow setting inputs,
as well as a hold input, are provided. Internal depletion
devices provide the normal timekeifpihg function.
Switching any of these inputs (one at a time) to VDD
results in the desired time setting function.
The three gates in the counter chain (Figure t) are
used for setting time. During normal operation, gate A
connects the shaper output to a prescaie counter (+50
or +60); gates B and C cascade the remaining counters.
Gate A is used to inhibit the input to the counters for
the duration of slow, fast or hold time-setting input
activity. Gate B is used to connect the shaper output
directly to a seconds counter (+60), the condition for
slow advance. Likewise, gate C connects the shaper
output directly to a minutes counter (+60) for fast
advance.
Fast set then, advances hours information at one hour
per second and slow set advances minutes information
at one minute per second.
" or 24-Hour Select Input: This input is used to pro-
gram the hours counter to divide by either 12 or 24,
thereby providing the desired display format. The
12-hoyr display format is selected by connecting this
input to VDD: leaving the input unconnected (internal
depletion device) selects the 24-hour format.
Output Multiplexer Operation: The seconds, minutes,
and hours counters continuously reflect the time of day.
Outputs from each counter (indicative of both units
and tens of seconds, minutes, and hours) are time-
division multiplexed to provide digit-sequential access
to the time data. Thus, instead of requiring 42 leads to
interconnect a 6-digit clock and its display (7 segments
per digit), only 13 output leads are required. The multi-
plexer is addressed by a multiplex divider decoder,
which is driven by a multiplex oscillator. The oscillator
and external timing components set the frequency of
the multiplexing function and, as controlled by the 4 or
trdigit select.input, the divider determines whether data
will be output for 4 or 6 digits. A "rtrblankintrcircu'it
suppresses the zero that would otherWiSe sometimes
appear in the ttiris-of-hours display; blanking is effective
only in the t24mur format. The multiplexer addresses
also become the display digit-enable outputs. The multi-
plexer outputs are applied to a decoder which is used
to address a programmable (code converting) ROM__.
This ROM generates the final output codes. i.e., BCD
and 2-segment. The sequential output. order is from
digit 6 (unit seconds) through digit 1 (tens of hours).
Multiplex Timing Input: The multiplex oscillator is
shown m Figure 2. Adding an external resistor and
capacitor to this circuit via the multiplex timing input
(as shown in Figure dir) produces a relaxation oscillator.
The waveform at this input is a quasi-sawtooth that is
squared by the shaping action of the Schmitt Trigger in
Figure 2. Figure 3 provides guidelines for selecting the
external. components relative to desired multiplex
frequency.
Figure 4. also illustrates two methods of synchronizing
the multiplex oscillator to an external timebase. The
external RC timing components may be omitted- and
this input may. be driven by an external timebase; the l
required logic levels ‘are the same as $0 or th Hz Input. ;
Reset: Applying VDD to this input resets the counters
to 0:00:00.00 in 12-hour format and 00:00:00.00 in
24-hour formats leaving the input unconnected (internal
depletion pull-up) selects normal operation. Proper
reset will be ensured when VDD to Vss slew rate is
no faster than one volt per microsecond. This can
be accomplished with a capacitor from the reset input
to vss.
4 or 6.Dlglt Select Input: Like the other control inputs,
this input is provided with an internal depletion pull-up
device. With no input connection the clock outputs data
for a 4digit display. Applying VDD lo this. inputtpro:
vides a 6-digit display.
Qgtput Enable Input: With this pin unconnected the
BCD and Tsegment outputs are enabled (via an internal
depletion pull-up). Switching VDD to' this input inhibits
these outputs. (Not applicable to MM5312, MM5313,
and MM5315 clocks. )
Output O_itouits: Figure 5a illustrates the circuit used
for the Fit-ir: and 7. -segment outputs. Figur'e 5b shows
the digit enable output circuit. Figure 6 illustrates
interfacing these outputs to standard and low power
TTL. Figures 7 and 8 illustrate methods of interfacing
these outputs to common anode and common cathode
LED displays, respectively. A method of interfacing
these clocks to gas discharge display tubes is shown in
Figure 9. When driving gas discharge displays which
enclose more than one digit in a common gas envelope,
it is necessary to inhibit the segment drive voltageis)
during inter-digit transitions. Figure 9 also illustrates a
method of generating a voltage for application to the
output enable input to accomplish the required inter-
digit blanking.
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Functional Description (Cont'd) :3 d..,'..'," . , ",',
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SHAPING
CIRCUIT
50/80 Hz
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SECONDS
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MULTIMEX
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FIGURE 1. MM5309 Digital Clock Block Diagram
50/60 PPS
OUTPUT Ott
som "I MULTIPLEX
Input on oscnunmn
Munmix OUTPUT
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I Dotted components added to shaping
Vss circuit to form multiplex oscillator
*Effectively
FIGURE 2. 50/60 Hz Shaping CirttuitlMutrrp1tm Oscillator
Functional Description (Cont'd) ' _ ji,
. MUX TIMING MES”!
F IGU RE 43. Relaxation Oscillator
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FIGURE an. External Time Base FIGURE ae. éxtemal Clock
Note. Free running frequency should be set to run slightly loWar than system frequency
_over temperature. External time base may be input or output.
. R=100k. . .
FIGURE 4. Synchronizing or Triggering Multiplcx Oscillators
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FIGURE Sa FIGURE tit,
FIGURE ti. Output circuits
MM5309, MM5311, MM5312, MM5313, MM5314, MM5315
Functional Description (Cont'd)
MOS to Low Pow TTL Interface
AIY TTL GAY!
Vcc'lv
For vss " B. VDD " 12, R " 10k
For vss -10to17V,Voo " Gnd, R " 3k
MOS " TTL Inurflco
ttst" "
Atty BATE:
mm T.'."
Ittt . "
Van I 42V
For vss " 5, Von . --12, R " 2,6k
Note. Digit select will drive TTL directly when
ti. -12 supplies are used.
FIGURE 6. lmnficlng TTL
Ifes I
EIAILE
tt HT?!"
vss - VDD " 0.6V
Where RL " in kn
And " " forward drop of LED
0.6V As vomge drop of transistor:
N " number of digits in display
IF " required average LED current
A A _-
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on Em)“.
EIAIL! " mm. m on m
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'Vss VDDDIZ VF 1.6V
Where Rt. it in kn
And VF " forward drop of LED
OSV " volnge drop of transistor:
N " number pt digits in diplay
IF " required average LED current
'Tramistors may be replaced by DM75491, DM75492.
DM8861, DM8883 or equivalent mont/digit driven.
FIGURE T. Interfacing Common Anode LED Display:
FIGURE 8. lm'lflcing Common Cathode LED OW
T -wl; ......,. s
Functional Deseription (Cont'd) _ 1'r " l,"", 'i,": 'v. l'
t - - - F"
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FIGURE 9. interface Pamplox ll' Neon Display Tube 'TM of Burroughs Corp. t,
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FIGURE 10. MM5309 Driving Gas Discharge Display, Tvpiml Applications
This datasheet has been :
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Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
MM5311 - product/mm5311?HQS=T|-nu||-nu|I-dscataIog-df-pf-null-wwe
MM5312 - product/mm5312?HQS=T|-nu||-nu|I-dscatalog-df—pf-nulI-wwe
MM5313 - product/mm5313?HQS=T|-nu|I-nu|I-dscatalog-df—pf—nulI-wwe
MM5314 - product/mm5314?HQS=T|-nu|I-nu|I-dscatalog-df-pf-nulI-wwe
MM5315 - product/mm5315?HQS=T|-nu||-nu|I-dscataIog-df-pf-null-wwe
MM5309N - product/mm5309n?HQS=TI-nuII-nul|-dscatalog-df—pf—nuII-wwe
MM5315N - product/mm5315n?HQS=TI-nuII-nulI-dscatalog-df-pf-null-wwe
MM5314N - product/mm5314n?HQS=T|-nu|I-nuII-dscatalog-df-pf-nuII-wwe
MM5313N - product/mm5313n?HQS=T|-nuII-null-dscataIog-df-pf-null-wwe
MM5312N - product/mm5312n?HQS=TI-nuII-nul|-dscatalog-df—pf—null-wwe
MM5311N - product/mm5311n?HQS=T|—nuII-nulI-dscatalog-df-pf-null-wwe
MM5309 - product/mm5309?HQS=TI—nu|I-null-dscataIog-df-pf-nuII-wwe
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