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MK48Z02B-12 |MK48Z02B12STN/a400avaiCMOS 2K x 8 XEROPOWER SRAM
MK48Z02B-15 |MK48Z02B15STN/a309avaiCMOS 2K x 8 XEROPOWER SRAM
MK48Z02B-20 |MK48Z02B20STN/a560avaiCMOS 2K x 8 XEROPOWER SRAM
MK48Z02B-25 |MK48Z02B25STN/a400avaiCMOS 2K x 8 XEROPOWER SRAM


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MK48Z02B-12-MK48Z02B-15-MK48Z02B-20-MK48Z02B-25
CMOS 2K x 8 XEROPOWER SRAM
SiE I) © 7929237 UUBBBHI: 33' DSGTH T-qt-aa-tu.
diti'rfzjl' $GS=W©MS©N MK48202
717® iW(C)RC(otlaE07RiC(j)2l%)(l MK48212
s G S-THONSON ,
CMOS 2K X 8 ZEROPOWER SRAM
u PREDICTED WORST CASE BATTERY LIFE OF
11 YEARS @ 70°C
II DATA RETENTION IN THE ABSENCE OF
n DATA SECURITY PROVIDED BY AUTOMATIC
WRITE PROTECTION DURING POWER
FAILURE
u + 5 VOLT ONLY READ/WRITE
" CONVENTIONAL SRAM WRITE CYCLES
a FULL CMOS-440mW ACTIVE ; 5.5mW
STANDBY
n 24-PIN DUAL IN LINE PACKAGE, JEDEC
PINOUTS Figure 1. Pin Connection
II READ-CYCLE TIME EQUALS WRITE-CYCLE
II LOW-BATTERY WARNING
u TWO POWER-FAIL DESELECT TRIP POINTS 17,
AVAILABLE:
- MK48202 4.75V k VPFD 2 4.50V A5
- MK48212 4.50V 2 VPFD 2 4.20V A4
DESCRIPTION 2:
The MK48202/12 is a 16,384-bit, Non-Voia- A1
tile Static RAM, organized 2K x 8 using A0
CMOS and an integral Lithium energy source. The 000
ZEROPOWERTM RAM has the characteristics of D Q1
a CMOS static RAM, with the important added
benefit of data being retained in the absence of D02
power. Data retention current is so small that a GND
miniature Lithium cell contained within the package
provides an errergy source to preserve data. Low VA00603
current drain has been attained by the use of a full
CMOS memory cell, novel analog support circuitry,
and carefully controlled junction leakage by an all
implanted CMOS process. Safeguards against in- N N MES
advertent data loss have been incorporated to main- Pl A
tain data integrity in the uncertain operating A0-A10
environment associated with power-up and power- -
down transients. The ZEROPOWER RAM can re- E Chip Enable
place existing 2K x 8 static RAM, directly conforming GND Ground
to the popular Byte Wide 24-pin DIP package
(JEDEC). MK48202/12 also matches the pinning of Vcc 5 Volts
2716 EPROM and 2Kx 8 EEPROM. Like other static - .
RAMs, there is no limit to the number of write cycles W Write Enable
that can be performed. Since the access time, read -
cycle, and write cycle are less than 250ns and G OutputEnable
require only + 5 volts, no additional support circuitry DQ0-DQ7 Data Inputs/Outputs
is needed for interface to a microprocessor.
PHDIP24 WITH BATTERY TOP HAT (B)
MK48202 19
MK48Z12 18
15 005
14 DQ4
13 J 003
(b\JOUI-bWN4
ULJI—ll—ll—lULJl—lLJl—II-l
l-ll—IHl-Il—ll—IHHl-Il-IHI—I
Address Inputs
February 1992 1/11
_ SiE I) D 7939837 MMM' 273 USGTH
MK48cua, MK4BZ1 2
S G S-THOVISON T-46-23-m
Flgure 2. Block Diagram
r- _____________________________ "I
I -- LITHIUM (zrczezo AO-A1o
l l T, CELL 2 K x tr l
I POWER
I RAM (r=riz) 000-007
I VOLTAGE SENSE P_OK CMOS I
I AND I -
----u- E
I SWITCHING CELL I -
I cmcunnv iRiR l w
I ---l- G
u. _.----.--------------.---------- _l
=r VRUUD792
TRUTH TABLE
Vcc E E W Mode 00
" X X Deselect High-Z
>VCC(min) VIL " " Read DOUT
VIL Ihre VIH Read High-Z
>Vso X X X Deselect High 2
Battery .
sVso X X X Back-up High-
2/11 §- scs-momson
w,, mGB9EMitWRtNtRX8
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