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MFRC500 01T |MFRC50001TPHIN/a6avaiThe 鈥淥riginal鈥?MIFARE reader solution
MFRC500 01T |MFRC50001TPHIN/a23avaiThe 鈥淥riginal鈥?MIFARE reader solution
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MFRC500 01T ,The 鈥淥riginal鈥?MIFARE reader solutionFeatures and benefits3.1 General Highly integrated analog circuitry for demodulating and decoding ..
MFRC500 01T ,The 鈥淥riginal鈥?MIFARE reader solutionFeatures and benefits3.1 General Highly integrated analog circuitry for demodulating and decoding ..
MFRC50001T ,The 鈥淥riginal鈥?MIFARE reader solutionGeneral descriptionThe MFRC500 is a highly integrated reader IC for contactless communication at 13 ..
MFRC50001T ,The 鈥淥riginal鈥?MIFARE reader solutionelectrical specifications and from a system and hardware viewpoint gives detailed information on ho ..
MFRC50001T ,The 鈥淥riginal鈥?MIFARE reader solution MFRC500The "Original" MIFARE reader solutionRev. 3.4 — 11 February 2014 Product data sheet048034 C ..
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MFRC500 01T-MFRC500 01T-MFRC50001T
The 鈥淥riginal鈥?MIFARE reader solution
1. Introduction
This data sheet describes the functionality of the MFRC500 Integrated Circuit (IC). It
includes the functional and electrical specifications and from a system and hardware
viewpoint gives detailed information on how to design-in the device.
Remark: The MFRC500 supports all variants of the MIFARE Classic, MIFARE 1K and

MIFARE 4K RF identification protocols. To aid readability throughout this data sheet, the
MIFARE Classic, MIFARE 1K and MIFARE 4K products and protocols have the generic
name MIFARE.
2. General description

The MFRC500 is a highly integrated reader IC for contactless communication at
13.56 MHz. The MFRC500 reader IC provides: outstanding modulation and demodulation for passive contactless communication a wide range of methods and protocols pin compatibility with the CLRC632, MFRC530, MFRC531 and SLRC400
All protocol layers of the ISO/IEC 14443 A are supported
The receiver module provides a robust and efficient demodulation/decoding circuitry
implementation for compatible transponder signals (see Section 9.10 on page 30). The
digital module, manages the complete ISO/IEC 14443 A standard framing and error
detection (parity and CRC). In addition, it supports the fast Crypto1 security algorithm for
authenticating the MIFARE products (see Section 9.12 on page 35).
The internal transmitter module (Section 9.9 on page 27) can directly drive an antenna
designed for a proximity operating distance up to 100 mm without any additional active
circuitry.
A parallel interface can be directly connected to any 8-bit microprocessor to ensure
reader/terminal design flexibility.
MFRC500
The "Original" MIFARE reader solution
Rev. 3.4 — 11 February 2014
Product data sheet
COMPANY PUBLIC
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
3. Features and benefits
3.1 General
Highly integrated analog circuitry for demodulating and decoding card response Buffered output drivers enable antenna connection using the minimum of external
components Proximity operating distance up to 100 mm Supports the ISO/IEC 14443 A standard, parts 1 to 4 Supports MIFARE Classic protocol Crypto1 and secure non-volatile internal key memory Pin-compatible with the CLRC632, MFRC530, MFRC531 and the SLRC400 Parallel microprocessor interface with internal address latch and IRQ line Flexible interrupt handling Automatic detection of parallel microprocessor interface type 64-byte send and receive FIFO buffer Hard reset with low power function Software triggered Power-down mode Programmable timer Unique serial number User programmable start-up configuration Bit-oriented and byte oriented framing Independent power supply pins for analog, digital and transmitter modules Internal oscillator buffer optimized for low phase jitter enables 13.56 MHz quartz
connection Clock frequency filtering 3.3 V operation for transmitter in short range and proximity applications
4. Applications
Electronic payment systems Identification systems Access control systems Subscriber services Banking systems Digital content systems
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
5. Quick reference data

6. Ordering information

Table 1. Quick reference data

Tamb ambient temperature 40 - +150 C
Tstg storage temperature 40 - +150 C
VDDD digital supply voltage 0.5 +5 +6 V
VDDA analog supply voltage 0.5 +5 +6 V
VDD(TVDD) TVDD supply voltage 0.5 +5 +6 V
Vi input voltage (absolute
value)
on any digital pin to DVSS 0.5 - VDDD + 0.5 V
on pin RX to AVSS 0.5 - VDDA + 0.5 V
ILI input leakage current 1.0 - +1.0 mA
IDD(TVDD) TVDD supply current continuous wave - - 150 mA
Table 2. Ordering information

MFRC50001T/0FE SO32 plastic small outline package; 32 leads; body width 7.5 mm SOT287-1
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
7. Block diagram

NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
8. Pinning information

8.1 Pin description

Table 3. Pin description
OSCIN I oscillator/clock inputs:
crystal oscillator input to the oscillator’s inverting amplifier
externally generated clock input; fclk(ext) = 13.56 MHz IRQ O interrupt request: generates an output signaling an interrupt event MFIN I ISO/IEC 14443 A MIFARE serial data interface input[2] MFOUT O serial data ISO/IEC 14443 A output TX1 O transmitter 1 modulated carrier output; 13.56 MHz TVDD P transmitter power supply for the TX1 and TX2 output stages TX2 O transmitter 2 modulated carrier output; 13.56 MHz TVSS G transmitter ground for the TX1 and TX2 output stages NCS I not chip select input is used to select and activate the MFRC500’s microprocessor
interface
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution

[1] Pin types: I= Input, O= Output, I/O= Input/Output, P= Power and G= Ground.
[2] The SLRC400 uses pin name SIGOUT for pin MFOUT. The MFRC500 functionality includes test functions for the SLRC400 using pin
MFOUT.
[3] These pins provide different functionality depending on the selected microprocessor interface type (see Section 9.1 on page 7 for
detailed information). DVSS G digital ground
13 to 20[3] D0 to D7 I/O 8-bit bidirectional data bus input/output on pins D0 to D7
AD0 to AD7 I/O 8-bit bidirectional address and data bus input/output on pins AD0 to AD7[3] ALE I address latch enable input for pins AD0 to AD5; HIGH latches the internal address I address strobe input for pins AD0 to AD5; HIGH latches the internal address
nAStrb I not address strobe input for pins AD0 to AD5; LOW latches the internal address[3] A0 I address line 0 is the address register bit 0 input
nWait O not wait output:
LOW starts an access cycle
HIGH ends an access cycle A1 I address line 1 is the address register bit 1 input[3] A2 I address line 2 is the address register bit 2 input DVDD P digital power supply AVDD P analog power supply for pins OSCIN, OSCOUT, RX, VMID and AUX AUX O auxiliary output is used to generate analog test signals. The output signal is
selected using the TestAnaSelect register’s TestAnaOutSel[4:0] bits AVSS G analog ground RX I receiver input is used as the card response input. The carrier is load modulated at
13.56 MHz, drawn from the antenna circuit VMID P internal reference voltage pin provides the internal reference voltage as a supply
Remark: It must be connected to a 100 nF block capacitor connected between pin

VMID and ground RSTPD I reset and power-down input:
HIGH: the internal current sinks are switched off, the oscillator is inhibited and
the input pads are disconnected
LOW (negative edge): start internal reset phase OSCOUT O crystal oscillator output for the oscillator’s inverting amplifier
Table 3. Pin description …continued
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
9. Functional description
9.1 Digital interface
9.1.1 Overview of supported microprocessor interfaces

The MFRC500 supports direct interfacing to various 8-bit microprocessors. Alternatively,
the MFRC500 can be connected to a PC’s Enhanced Parallel Port (EPP). Table 4 shows
the parallel interface signals supported by the MFRC500.
9.1.2 Automatic microprocessor interface detection

After a Power-On or Hard reset, the MFRC500 resets the parallel microprocessor
interface mode and detects the microprocessor interface type.
The MFRC500 identifies the microprocessor interface using the logic levels on the control
pins. This is performed using a combination of fixed pin connections and the dedicated
Initialization routine (see Section 9.7.4 on page 25).
Table 4. Supported microprocessor and EPP interface signals

Separated read and
write strobes
control NRD, NWR, NCS NRD, NWR, NCS, ALE
address A0, A1, A2 AD0, AD1, AD2, AD3, AD4, AD5
data D0 to D7 AD0 to AD7
Common read and write
strobe
control R/NW, NDS, NCS R/NW, NDS, NCS, AS
address A0, A1, A2 AD0, AD1, AD2, AD3, AD4, AD5
data D0 to D7 AD0 to AD7
Common read and write
strobe with handshake
(EPP)
control - nWrite, nDStrb, nAStrb, nWait
address - AD0, AD1, AD2, AD3, AD4, AD5
data - AD0 to AD7
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
9.1.3 Connection to different microprocessor types

The connection to various microprocessor types is shown in Table5.
9.1.3.1 Separate read and write strobe

Refer to Section 13.4.1 on page 86 for timing specification.
Table 5. Connection scheme for detecting the parallel interface type

ALE HIGH ALE HIGH AS nAStrb A2 LOW A2 LOW HIGH A1 HIGH A1 HIGH HIGH A0 HIGH A0 LOW nWait
NRD NRD NRD NDS NDS nDStrb
NWR NWR NWR R/NW R/NW nWrite
NCS NCS NCS NCS NCS LOW
D7 to D0 D7 to D0 AD7 to AD0 D7 to D0 AD7 to AD0 AD7 to AD0
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
9.1.3.2 Common read and write strobe

Refer to Section 13.4.2 on page 87 for timing specification.
9.1.3.3 Common read and write strobe: EPP with handshake

Refer to Section 13.4.3 on page 88 for timing specification.
Remark: In the EPP standard a chip select signal is not defined. To cover this situation,

the status of the NCS pin can be used to inhibit the nDStrb signal. If this inhibitor is not
used, it is mandatory that pin NCS is connected to pin DVSS.
Remark: After each Power-On or Hard reset, the nWait signal on pin A0 is

high-impedance. nWait is defined as the first negative edge applied to the nAStrb pin after
the reset phase. The MFRC500 does not support Read Address Cycle.
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
9.2 Memory organization of the EEPROM
Table 6. EEPROM memory organization diagram 0 00h to 0Fh R product
information field
Section 9.2.1 on page11 1 10h to 1Fh R/W StartUp register
initialization file
Section 9.2.2.1 on page11 2 20h to 2Fh R/W 3 30h to 3Fh R/W register
initialization file
Section 9.2.2.3 “Register
initialization file (read/write)”
on page 134 4 40h to 4Fh R/W 5 50h to 5Fh R/W 6 60h to 6Fh R/W 7 70h to 7Fh R/W 8 80h to 8Fh W keys for Crypto1 Section 9.2.3 on page13
9990h to 9Fh W A A0h to AFh W B B0h to BFh W C C0h to CFh W D D0h to DFh W E E0h to EFh W F F0h to FFh W 10 100h to 10Fh W 11 110h to 11Fh W 12 120h to 12Fh W 13 130h to 13Fh W 14 140h to 14Fh W 15 150h to 15Fh W 16 160h to 16Fh W 17 170h to 17Fh W 18 180h to 18Fh W 19 190h to 19Fh W 1A 1A0h to 1AFh W 1B 1B0h to 1BFh W 1C 1C0h to 1CFh W 1D 1D0h to 1DFh W 1E 1E0h to 1EFh W 1F 1F0h to 1FFh W
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
9.2.1 Product information field (read only)

[1] Byte 4 contains the current version number.
9.2.2 Register initialization files (read/write)

Register initialization from address 10h to address 2Fh is performed automatically during
the initializing phase (see Section 9.7.3 on page 25) using the StartUp register
initialization file.
In addition, the MFRC500 registers can be initialized using values from the register
initialization file when the LoadConfig command is executed (see Section 11.4.1 on
page 79).
Remark: The following points apply to initialization:
the Page register (addressed using 10h, 18h, 20h, 28h) is skipped and not initialized. PreSetxx registers: do not change. all reserved register bits set to logic 0: do not change.
9.2.2.1 StartUp register initialization file (read/write)

The EEPROM memory block address 1 and 2 contents are used to automatically set the
register subaddresses 10h to 2Fh during the initialization phase. The default values stored
in the EEPROM during production are shown in Section 9.2.2.2 “Factory default StartUp
register initialization file”.
Table 7. Product information field byte allocation
Table 8. Product information field byte description
CRC R - the content of the product information field
is secured using a CRC byte which is
checked during start-up
14 to 12 Internal R - three bytes for internal trimming parameters
11 to 8 Product Serial Number R - a unique four byte serial number for the
device
7 to 5 reserved R -
4 to 0 Product Type
Identification - the MFRC500 is a member of a new family
of highly integrated reader ICs. Each
member of the product family has a unique
product type identification. The value of the
product type identification is shown in
Table9.
Table 9. Product type identification definition
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution

The byte assignment is shown in Table 10.
9.2.2.2 Factory default StartUp register initialization file

During the production tests, the StartUp register initialization file is initialized using the
default values shown in Table 11. During each power-up and initialization phase, these
values are written to the MFRC500’s registers.
Table 10. Byte assignment for register initialization at start-up

10h (block 1, byte 0) 10h skipped
11h 11h copied …
2Fh (block 2, byte 15) 2Fh copied
Table 11. Shipment content of StartUp configuration file

10h 10h 00h Page free for user
11h 11h 58h TxControl transmitter pins TX1 and TX2 are switched off, bridge driver
configuration, modulator driven from internal digital circuitry
12h 12h 3Fh CwConductance source resistance of TX1 and TX2 is set to minimum
13h 13h 3Fh PreSet13 -
14h 14h 19h PreSet14 -
15h 15h 13h ModWidth pulse width for Miller pulse encoding is set to standard configuration
16h 16h 00h PreSet16 -
17h 17h 00h PreSet17 -
18h 18h 00h Page free for user
19h 19h 73h RxControl1 ISO/IEC 14443 A is set and internal amplifier gain is maximum
1Ah 1Ah 08h DecoderControl bit-collisions always evaluate to HIGH in the data bit stream
1Bh 1Bh ADh BitPhase BitPhase[7:0] is set to standard configuration
1Ch 1Ch FFh RxThreshold MinLevel[3:0] and CollLevel[3:0] are set to maximum
1Dh 1Dh 00h PreSet1D -
1Eh 1Eh 41h RxControl2 use Q-clock for the receiver, automatic receiver off is switched on,
decoder is driven from internal analog circuitry
1Fh 1Fh 00h ClockQControl automatic Q-clock calibration is switched on
20h 20h 00h Page free for user
21h 21h 06h RxWait frame guard time is set to six bit-clocks
22h 22h 03h ChannelRedundancy channel redundancy is set using ISO/IEC 14443A
23h 23h 63h CRCPresetLSB CRC preset value is set using ISO/IEC 14443A
24h 24h 63h CRCPresetMSB CRC preset value is set using ISO/IEC 14443A
25h 25h 00h PreSet25 -
26h 26h 00h MFOUTSelect pin MFOUT is set LOW
27h 27h 00h PreSet27 -
28h 28h 00h Page free for user
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
9.2.2.3 Register initialization file (read/write)

The EEPROM memory content from block address 3 to 7 can initialize register
subaddresses 10h to 2Fh when the LoadConfig command is executed (see
Section 11.4.1 on page 79). This command requires the EEPROM starting byte address
as a two byte argument for the initialization procedure.
The byte assignment is shown in Table 12.
The register initialization file is large enough to hold values for two initialization sets and
up to one block (16-byte) of user data.
Remark: The register initialization file can be read/written by users and these bytes can

be used to store other user data.
After each power-up, the default configuration enables the MIFARE and ISO/IEC 14443A
protocol.
9.2.3 Crypto1 keys (write only)

MIFARE security requires specific cryptographic keys to encrypt data stream
communication on the contactless interface. These keys are called Crypto1 keys.
9.2.3.1 Key format

Keys stored in the EEPROM are written in a specific format. Each key byte must be split
into lower four bits k0 to k3 (lower nibble) and the higher four bits k4 to k7 (higher nibble).
Each nibble is stored twice in one byte and one of the two nibbles is bit-wise inverted. This
format is a precondition for successful execution of the LoadKeyE2 (see Section 11.6.1 on
page 81) and LoadKey commands (see Section 11.6.2 on page 81).
29h 29h 08h FIFOLevel WaterLevel[5:0] FIFO buffer warning level is set to standard
configuration
2Ah 2Ah 07h TimerClock TPreScaler[4:0] is set to standard configuration, timer unit restart
function is switched off
2Bh 2Bh 06h TimerControl Timer is started at the end of transmission, stopped at the beginning
of reception
2Ch 2Ch 0Ah TimerReload TReloadValue[7:0]: the timer unit preset value is set to standard
configuration
2Dh 2Dh 02h IRQPinConfig pin IRQ is set to high-impedance
2Eh 2Eh 00h PreSet2E -
2Fh 2Fh 00h PreSet2F -
Table 11. Shipment content of StartUp configuration file …continued
Table 12. Byte assignment for register initialization at startup

EEPROM starting byte address 10h skipped
EEPROM + 1 starting byte address 11h copied
EEPROM + 31 starting byte address 2Fh copied
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution

Using this format, 12 bytes of EEPROM memory are needed to store a 6-byte key. This is
shown in Figure6.
Example: The value for the key must be written to the EEPROM.
If the key was: A0h A1h A2h A3h A4h A5h then 5Ah F0h 5Ah E1h 5Ah D2h 5Ah C3h 5Ah B4h 5Ah A5h would be written.
Remark: It is possible to load data for other key formats into the EEPROM key storage

location. However, it is not possible to validate card authentication with data which will
cause the LoadKeyE2 command (see Section 11.6.1 on page 81) to fail.
9.2.3.2 Storage of keys in the EEPROM

The MFRC500 reserves 384 bytes of memory in the EEPROM for the Crypto1 keys. No
memory segmentation is used to mirror the 12-byte structure of key storage. Thus, every
byte of the dedicated memory area can be the start of a key.
Example: If the key loading cycle starts at the last byte address of an EEPROM block, (for

example, key byte 0 is stored at 12Fh), the next bytes are stored in the next EEPROM
block, for example, key byte 1 is stored at 130h, byte 2 at 131h up to byte 11 at 13Ah.
Based on the 384 bytes of memory and a single key needing 12 bytes, then up to 32
different keys can be stored in the EEPROM.
Remark: It is not possible to load a key exceeding the EEPROM byte location 1FFh.
9.3 FIFO buffer

An 8 64 bit FIFO buffer is used in the MFRC500 to act as a parallel-to-parallel converter.
It buffers both the input and output data streams between the microprocessor and the
internal circuitry of the MFRC500. This makes it possible to manage data streams up to
64 bytes long without needing to take timing constraints into account.
9.3.1 Accessing the FIFO buffer
9.3.1.1 Access rules

The FIFO buffer input and output data bus is connected to the FIFOData register. Writing
to this register stores one byte in the FIFO buffer and increments the FIFO buffer write
pointer. Reading from this register shows the FIFO buffer contents stored at the FIFO
buffer read pointer and increments the FIFO buffer read pointer. The distance between the
write and read pointer can be obtained by reading the FIFOLength register.
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution

When the microprocessor starts a command, the MFRC500 can still access the FIFO
buffer while the command is running. Only one FIFO buffer has been implemented which
is used for input and output. Therefore, the microprocessor must ensure that there are no
inadvertent FIFO buffer accesses. Table 13 gives an overview of FIFO buffer access
during command processing.
9.3.2 Controlling the FIFO buffer

In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be
reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit
FIFOOvfl is cleared and the stored bytes are no longer accessible. This enables the FIFO
buffer to be written with another 64 bytes of data.
9.3.3 FIFO buffer status information

The microprocessor can get the following FIFO buffer status data: the number of bytes stored in the FIFO buffer: bits FIFOLength[6:0] the FIFO buffer full warning: bit HiAlert the FIFO buffer empty warning: bit LoAlert the FIFO buffer overflow warning: bit FIFOOvfl.
Remark: Setting the FlushFIFO bit clears the FIFOOvfl bit.

The MFRC500 can generate an interrupt signal when: bit LoAlertIRq is set to logic 1 and bit LoAlert= logic 1, pin IRQ is activated. bit HiAlertIRq is set to logic 1 and bit HiAlert= logic 1, pin IRQ activated.
The HiAlert flag bit is set to logic 1 only when the WaterLevel[5:0] bits or less can be
stored in the FIFO buffer. The trigger is generated by Equation1:
Table 13. FIFO buffer access

StartUp - -
Idle - -
Transmit yes -
Receive - yes
Transceive yes yes the microprocessor has to know the state of the
command (transmitting or receiving)
WriteE2 yes -
ReadE2 yes yes the microprocessor has to prepare the arguments,
afterwards only reading is allowed
LoadKeyE2 yes -
LoadKey yes -
Authent1 yes -
Authent2 - -
LoadConfig yes -
CalcCRC yes -
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution

(1)
The LoAlert flag bit is set to logic 1 when the FIFOLevel register’s WaterLevel[5:0] bits or
less are stored in the FIFO buffer. The trigger is generated by Equation2:
(2)
9.3.4 FIFO buffer registers and flags

Table 14 shows the related FIFO buffer flags in alphabetic order.
9.4 Interrupt request system

The MFRC500 indicates interrupt events by setting the PrimaryStatus register bit IRq (see
Section 10.5.1.4 “PrimaryStatus register” on page 45) and activating pin IRQ. The signal
on pin IRQ can be used to interrupt the microprocessor using its interrupt handling
capabilities ensuring efficient microprocessor software.
9.4.1 Interrupt sources overview

Table 15 shows the integrated interrupt flags, related source and setting condition. The
interrupt TimerIRq flag bit indicates an interrupt set by the timer unit. Bit TimerIRq is set
when the timer decrements from one down to zero (bit TAutoRestart disabled) or from one
to the TReLoadValue[7:0] with bit TAutoRestart enabled.
Bit TxIRq indicates interrupts from different sources and is set as follows: the transmitter automatically sets the bit TxIRq interrupt when it is active and its state
changes from sending data to transmitting the end of frame pattern the CRC coprocessor sets the bit TxIRq after all data from the FIFO buffer has been
processed indicated by bit CRCReady= logic 1 when EEPROM programming is finished, the bit TxIRq is set and is indicated by bit
E2Ready= logic 1
The RxIRq flag bit indicates an interrupt when the end of the received data is detected.
The IdleIRq flag bit is set when a command finishes and the content of the Command
register changes to Idle.
Table 14. Associated FIFO buffer registers and flags

FIFOLength[6:0] FIFOLength 6 to 0 04h
FIFOOvfl ErrorFlag 4 0Ah
FlushFIFO Control 0 09h
HiAlert PrimaryStatus 1 03h
HiAlertIEn InterruptEn 1 06h
HiAlertIRq InterruptRq 1 07h
LoAlert PrimaryStatus 0 03h
LoAlertIEn InterruptEn 0 06h
LoAlertIRq InterruptRq 0 07h
WaterLevel[5:0] FIFOLevel 5 to 0 29h
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution

When the FIFO buffer reaches the HIGH-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 on page 15) and bit HiAlert= logic 1, then the HiAlertIRq flag bit is set to
logic1.
When the FIFO buffer reaches the LOW-level indicated by the WaterLevel[5:0] value (see
Section 9.3.3 and bit LoAlert= logic 1, then LoAlertIRq flag bit is set to logic1.
9.4.2 Interrupt request handling
9.4.2.1 Controlling interrupts and getting their status

The MFRC500 informs the microprocessor about the interrupt request source by setting
the relevant bit in the InterruptRq register. The relevance of each interrupt request bit as
source for an interrupt can be masked by the InterruptEn register interrupt enable bits.
If an interrupt request flag is set to logic 1 (showing that an interrupt request is pending)
and the corresponding interrupt enable flag is set, the PrimaryStatus register IRq flag bit is
set to logic 1. Different interrupt sources can activate simultaneously and because of this,
all interrupt request bits are OR’ed, coupled to the IRq flag and then forwarded to pin IRQ.
9.4.2.2 Accessing the interrupt registers

The interrupt request bits are automatically set by the MFRC500’s internal state
machines. In addition, the microprocessor can also set or clear the interrupt request bits
as required.
A special implementation of the InterruptRq and InterruptEn registers enables changing
an individual bit status without influencing any other bits. If an interrupt register is set to
logic 1, bit SetIxx and the specific bit must both be set to logic 1 at the same time. Vice
versa, if a specific interrupt flag is cleared, zero must be written to the SetIxx and the
interrupt register address must be set to logic 1 at the same time.
If a content bit is not changed during the setting or clearing phase, zero must be written to
the specific bit location.
Table 15. Interrupt sources

TimerIRq timer unit timer counts from 1 to 0
TxIRq transmitter a data stream, transmitted to the card, ends
CRC coprocessor all data from the FIFO buffer has been processed
EEPROM all data from the FIFO buffer has been
programmed
RxIRq receiver a data stream, received from the card, ends
IdleIRq Command register command execution finishes
HiAlertIRq FIFO buffer FIFO buffer is full
LoAlertIRq FIFO buffer FIFO buffer is empty
Table 16. Interrupt control registers

InterruptEn SetIEn reserved TimerIEn TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn
InterruptRq SetIRq reserved TimerIRq TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
Example: Writing 3Fh to the InterruptRq register clears all bits. SetIRq is set to logic 0

while all other bits are set to logic 1. Writing 81h to the InterruptRq register sets LoAlertIRq
to logic 1 and leaves all other bits unchanged.
9.4.3 Configuration of pin IRQ

The logic level of the IRq flag bit is visible on pin IRQ. The signal on pin IRQ can also be
controlled using the following IRQPinConfig register bits. bit IRQInv: the signal on pin IRQ is equal to the logic level of bit IRq when this bit is set
to logic 0. When set to logic 1, the signal on pin IRQ is inverted with respect to bit IRq. bit IRQPushPull: when set to logic 1, pin IRQ has CMOS output characteristics. When
it is set to logic 0, it is an open-drain output which requires an external resistor to
achieve a HIGH-level at pin IRQ.
Remark: During the reset phase (see Section
9.7.2 on page 25) bit IRQInv is set to
logic 1 and bit IRQPushPull is set to logic 0. This results in a high-impedance on pin IRQ.
9.4.4 Register overview interrupt request system

Table 17 shows the related interrupt request system flags in alphabetically. Table 17. Associated Interrupt request system registers and flags
HiAlertIEn InterruptEn 1 06h
HiAlertIRq InterruptRq 1 07h
IdleIEn InterruptEn 2 06h
IdleIRq InterruptRq 2 07h
IRq PrimaryStatus 3 03h
IRQInv IRQPinConfig 1 07h
IRQPushPull IRQPinConfig 0 07h
LoAlertIEn InterruptEn 0 06h
LoAlertIRq InterruptRq 0 07h
RxIEn InterruptEn 3 06h
RxIRq InterruptRq 3 07h
SetIEn InterruptEn 7 06h
SetIRq InterruptRq 7 07h
TimerIEn InterruptEn 5 06h
TimerIRq InterruptRq 5 07h
TxIEn InterruptEn 4 06h
TxIRq InterruptRq 4 07h
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9.5 Timer unit

The timer derives its clock from the 13.56 MHz on-board chip clock. The microprocessor
can use this timer to manage timing-relevant tasks.
The timer unit may be used in one of the following configurations: Timeout counter WatchDog counter Stopwatch Programmable one shot Periodical trigger
The timer unit can be used to measure the time interval between two events or to indicate
that a specific timed event occurred. The timer is triggered by events but does not
influence any event (e.g. a time-out during data receiving does not automatically influence
the reception process). Several timer related flags can be set and these flags can be used
to generate an interrupt.
9.5.1 Timer unit implementation
9.5.1.1 Timer unit block diagram

Figure 7 shows the block diagram of the timer module.
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The timer unit is designed, so that events when combined with enabling flags start or stop
the counter. For example, setting bit TStartTxBegin= logic 1 enables control of received
data with the timer unit. In addition, the first received bit is indicated by the TxBegin event.
This combination starts the counter at the defined TReloadValue[7:0].
The timer stops automatically when the counter value is equal to zero or if a defined stop
event happens. Controlling the timer unit
The main part of the timer unit is a down counter. As long as the down counter value is not
zero, it decrements its value with each timer clock cycle.
If the TAutoRestart flag is enabled, the timer does not decrement down to zero. On
reaching value 1, the timer reloads the next clock function with the TReloadValue[7:0].
The timer is started immediately by loading a value from the TimerReload register into the
counter module.
This is activated by one of the following events:
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transmission of the first bit to the card (TxBegin event) with bit TStartTxBegin = logic1 transmission of the last bit to the card (TxEnd event) with bit TStartTxEnd= logic1 bit TStartNow is set to logic 1 by the microprocessor
Remark: Every start event reloads the timer from the TimerReload register which

re-triggers the timer unit.
The timer can be configured to stop on one of the following events: receipt of the first valid bit from the card (RxBegin event) with bit
TStopRxBegin= logic1 receipt of the last bit from the card (RxEnd event) with bit TStopRxEnd= logic1 the counter module has decremented down to zero and bit TAutoRestart= logic0 bit TStopNow is set to logic 1 by the microprocessor.
Loading a new value, e.g. zero, into the TimerReload register or changing the timer unit
while it is counting will not immediately influence the counter. In both cases, this is
because this register only affects the counter content after a start event.
If the counter is stopped when bit TStopNow is set, no TimerIRq is flagged.
9.5.1.3 Timer unit clock and period

The timer unit clock is derived from the 13.56 MHz on-board chip clock using the
programmable divider. Clock selection is made using the TimerClock register
TPreScaler[4:0] bits based on Equation3:
(3)
The values for the TPreScaler[4:0] bits are between 0 and 21 which results in a minimum
periodic time (TTimerClock) of between 74 ns and 150 ms.
The time period elapsed since the last start event is calculated using Equation4:
(4)
This results in a minimum time period (tTimer) of between 74 ns and 40 s.
9.5.1.4 Timer unit status

The SecondaryStatus register’s TRunning bit shows the timer’s status. Configured start
events start the timer at the TReloadValue[7:0] and change the status flag TRunning to
logic 1. Conversely, configured stop events stop the timer and set the TRunning status
flag to logic 0. As long as status flag TRunning is set to logic 1, the TimerValue register
changes on the next timer unit clock cycle.
The TimerValue[7:0] bits can be read directly from the TimerValue register.
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9.5.2 Using the timer unit functions
9.5.2.1 Time-out and WatchDog counters

After starting the timer using TReloadValue[7:0], the timer unit decrements the TimerValue
register beginning with a given start event. If a given stop event occurs, such as a bit
being received from the card, the timer unit stops without generating an interrupt.
If a stop event does not occur, such as the card not answering within the expected time,
the timer unit decrements down to zero and generates a timer interrupt request. This
signals to the microprocessor the expected event has not occurred within the given time
(tTimer).
9.5.2.2 Stopwatch

The time (tTimer) between a start and stop event is measured by the microprocessor using
the timer unit. Setting the TReloadValue register triggers the timer which in turn, starts to
decrement. If the defined stop event occurs, the timer stops. The time between start and
stop is calculated by the microprocessor using Equation 5 when the time does not
decrement down to zero.
(5)
9.5.2.3 Programmable one shot timer and periodic trigger
Programmable one shot timer: The microprocessor starts the timer unit and waits for

the timer interrupt. The interrupt occurs after the time specified by tTimer.
Periodic trigger: If the microprocessor sets the TAutoRestart bit, it generates an interrupt

request after every tTimer cycle.
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9.5.3 Timer unit registers

Table 18 shows the related flags of the timer unit in alphabetical order.
9.6 Power reduction modes
9.6.1 Hard power-down

Hard power-down is enabled when pin RSTPD is HIGH. This turns off all internal current
sinks including the oscillator. All digital input buffers are separated from the input pads and
defined internally (except pin RSTPD itself). The output pins are frozen at a given value.
The status of all pins during a hard power-down is shown in Table 19.
Table 18. Associated timer unit registers and flags

TAutoRestart TimerClock 5 2Ah
TimerValue[7:0] TimerValue 7 to 0 0Ch
TReloadValue[7:0] TimerReload 7 to 0 2Ch
TPreScaler[4:0] TimerClock 4 to 0 2Ah
TRunning SecondaryStatus 7 05h
TStartNow Control 1 09h
TStartTxBegin TimerControl 0 2Bh
TStartTxEnd TimerControl 1 2Bh
TStopNow Control 2 09h
TStopRxBegin TimerControl 2 2Bh
TStopRxEnd TimerControl 3 2Bh
Table 19. Signal on pins during Hard power-down

OSCIN 1 I not separated from input, pulled to AVSS
IRQ 2 O high-impedance
MFIN 3 I separated from input
MFOUT 4 O LOW
TX1 5 O HIGH, if bit TX1RFEn = logic 1
LOW, if bit TX1RFEn = logic 0
TX2 7 O HIGH, only if bit TX2RFEn = logic 1 and bit
TX2Inv= logic 0
otherwise LOW
NCS 9 I separated from input
NWR 10 I separated from input
NRD 11 I separated from input
D0 to D7 13 to 20 I/O separated from input
ALE 21 I separated from input 22 I/O separated from input 23 I separated from input 24 I separated from input
AUX 27 O high-impedance
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9.6.2 Soft power-down mode

Soft power-down mode is entered immediately using the Control register bit PowerDown.
All internal current sinks, including the oscillator buffer, are switched off. The digital input
buffers are not separated from the input pads and keep their functionality. In addition, the
digital output pins do not change their state.
After resetting the Control register bit PowerDown, the bit indicating Soft power-down
mode is only cleared after 512 clock cycles. Resetting it does not immediately clear it. The
PowerDown bit is automatically cleared when the Soft power-down mode is exited.
Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to

become stable. This is because the internal oscillator is supplied by VDDA and any clock
cycles will not be detected by the internal logic until VDDA is stable.
9.6.3 Standby mode

The Standby mode is immediately entered when the Control register StandBy bit is set. All
internal current sinks, including the internal digital clock buffer are switched off. However,
the oscillator buffer is not switched off.
The digital input buffers are not separated by the input pads, keeping their functionality
and the digital output pins do not change their state. In addition, the oscillator does not
need time to wake-up.
After resetting the Control register StandBy bit, it takes four clock cycles on pin OSCIN for
Standby mode to exit. Resetting bit StandBy does not immediately clear it. It is
automatically cleared when the Standby mode is exited.
9.6.4 Automatic receiver power-down

It is a power saving feature to switch off the receiver circuit when it is not needed. Setting
bit RxAutoPD= logic 1, automatically powers down the receiver when it is not in use.
Setting bit RxAutoPD= logic 0, keeps the receiver continuously powered up. 29 I not changed
VMID 30 A pulled to VDDA
RSTPD 31 I not changed
OSCOUT 32 O HIGH
Table 19. Signal on pins during Hard power-down …continued
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9.7 StartUp phase

The events executed during the StartUp phase are shown in Figure8.
9.7.1 Hard power-down phase

The hard power-down phase is active during the following cases: a Power-On Reset (POR) caused by power-up on pins DVDD or AVDD activated
when VDDD or VDDA is below the relevant analog/digital reset threshold. a HIGH-level on pin RSTPD which is active while pin RSTPD is HIGH. The HIGH level
period on pin RSTPD must be at least 100 s (tPD  100 s). Shorter phases will not
necessarily result in the reset phase (treset). The rising or falling edge slew rate on pin
RSTPD is not critical because pin RSTPD is a Schmitt trigger input.
9.7.2 Reset phase

The reset phase automatically follows the Hard power-down. Once the oscillator is
running stably, the reset phase takes 512 clock cycles. During the reset phase, some
register bits are preset by hardware. The respective reset values are given in the
description of each register (see Section 10.5 on page 43).
Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to

become stable. This is because the internal oscillator is supplied by VDDA and any clock
cycles will not be detected by the internal logic until VDDA is stable.
9.7.3 Initialization phase

The initialization phase automatically follows the reset phase and takes 128 clock cycles.
During the initializing phase the content of the EEPROM blocks 1 and 2 is copied into the
register subaddresses 10h to 2Fh (see Section 9.2.2 on page 11).
Remark: During the production test, the MFRC500 is initialized with default configuration

values. This reduces the microprocessor’s configuration time to a minimum.
9.7.4 Initializing the parallel interface type

A different initialization sequence is used for each microprocessor. This enables detection
of the correct microprocessor interface type and synchronization of the microprocessor’s
and the MFRC500’s start-up. See Section 9.1.3 on page 8 for detailed information on the
different connections for each microprocessor interface type.
During StartUp phase, the command value is set to 3Fh once the oscillator attains clock
frequency stability at an amplitude of > 90 % of the nominal 13.56 MHz clock frequency. At
the end of the initialization phase, the MFRC500 automatically switches to idle and the
command value changes to 00h.
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To ensure correct detection of the microprocessor interface, the following sequence is
executed: the Command register is read until the 6-bit register value is 00h. On reading the 00h
value, the internal initialization phase is complete and the MFRC500 is ready to be
controlled write 80h to the Page register to initialize the microprocessor interface read the Command register. If it returns a value of 00h, the microprocessor interface
was successfully initialized write 00h to the Page registers to activate linear addressing mode.
9.8 Oscillator circuit

The clock applied to the MFRC500 acts as a time basis for the synchronous system
encoder and decoder. The stability of the clock frequency is an important factor for correct
operation. To obtain highest performance, clock jitter must be as small as possible. This is
best achieved by using the internal oscillator buffer with the recommended circuitry.
If an external clock source is used, the clock signal must be applied to pin OSCIN. In this
case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock
quality has been verified. It must meet the specifications described in Section 13.4.4 on
page 90.
Remark: We do not recommend using an external clock source.
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9.9 Transmitter pins TX1 and TX2

The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an
envelope signal. It can be used to drive an antenna directly, using minimal passive
components for matching and filtering (see Section 15.1 on page 91). To enable this, the
output circuitry is designed with a very low-impedance source resistance. The TxControl
register is used to control the TX1 and TX2 signals.
9.9.1 Configuring pins TX1 and TX2

TX1 pin configurations are described in Table 20.
TX2 pin configurations are described in Table 21.
Table 20. Pin TX1 configurations
X X LOW (GND) 0 0 13.56 MHz carrier frequency modulated 0 1 13.56 MHz carrier frequency 0 LOW 1 1 13.56 MHz energy carrier
Table 21. Pin TX2 configurations
X X X LOW 0 0 0 0 13.56 MHz carrier frequency
modulated 0 0 0 1 13.56 MHz carrier frequency 0 0 1 0 13.56 MHz carrier frequency modulated, 180 phase-shift
relative to TX1 0 0 1 1 13.56 MHz carrier frequency,
180 phase-shift relative to TX1 0 1 0 X 13.56 MHz carrier frequency 0 1 1 X 13.56 MHz carrier frequency,
180 phase-shift relative to TX1 0 0 0 LOW 1 0 0 1 13.56 MHz carrier frequency 0 1 0 HIGH 1 0 1 1 13.56 MHz carrier frequency,
180 phase-shift relative to TX1 1 1 0 X 13.56 MHz carrier frequency 1 1 1 X 13.56 MHz carrier frequency,
180 phase-shift relative to TX1
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9.9.2 Antenna operating distance versus power consumption

Using different antenna matching circuits (by varying the supply voltage on the antenna
driver supply pin TVDD), it is possible to find the trade-off between maximum effective
operating distance and power consumption. Different antenna matching circuits are
described in the Application note “MIFARE Design of MFRC500 Matching Circuit and
Antennas”.
9.9.3 Antenna driver output source resistance

The output source conductance of pins TX1 and TX2 can be adjusted between 1  and
100  using the CwConductance register GsCfgCW[5:0] bits.
The output source conductance of pins TX1 and TX2 during the modulation phase can be
adjusted between 1  and 100  using the ModConductance register GsCfgMod[5:0] bits.
The values are relative to the reference resistance (RS(ref)) which is measured during the
production test and stored in the MFRC500 EEPROM. It can be read from the product
information field (see Section 9.2.1 on page 11). The electrical specification can be found
in Section 13.3.3 on page 86.
9.9.3.1 Source resistance table
Table 22. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW or GsCfgMod
MANT = Mantissa; EXP= Exponent.
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9.9.3.2 Calculating the relative source resistance

The reference source resistance RS(ref) can be calculated using Equation6.
(6)
The reference source resistance (RS(ref)) during the modulation phase can be calculated
using ModConductance register’s GsCfgMod[5:0].
9.9.3.3 Calculating the effective source resistance
Wiring resistance (RS(wire)): Wiring and bonding add a constant offset to the driver

resistance that is relevant when pins TX1 and TX2 are switched to low-impedance. The
additional resistance for pin TX1 (RS(wire)TX1) can be set approximately as shown in
Equation7.
(7)
Effective resistance (RSx): The source resistances of the driver transistors (RsMaxP

byte) read from the Product Information Field (see Section 9.2.1 on page 11) are
measured during the production test with CwConductance register’s
GsCfgCW[5:0]= 01h.
To calculate the driver resistance for a specific value set in GsCfgMod[5:0], use
Equation8.
(8)
9.9.4 Pulse width

The envelope carries the data signal information that is transmitted to the card. It is an
encoded data signal based on the Miller code. In addition, each pause of the Miller
encoded signal is again encoded as a pulse of a fixed width. The width of the pulse is
Table 22. TX1 and TX2 source resistance of n-channel driver transistor against GsCfgCW or GsCfgMod …continued

MANT = Mantissa; EXP= Exponent.
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adjusted using the ModWidth register. The pulse width (tw) is calculated using Equation9
where the frequency constant (fclk)= 13.56 MHz.
(9)
9.10 Receiver circuit

The MFRC500 uses an integrated quadrature demodulation circuit enabling it to extract
the ISO/IEC 14443 A compliant subcarrier from the 13.56 MHz ASK modulated signal
applied to pin RX.
The quadrature demodulator uses two different clocks (Q-clock and I-clock) with a
phase-shift of 90 between them. Both resulting subcarrier signals are amplified, filtered
and forwarded to the correlation circuitry. The correlation results are evaluated, digitized
and then passed to the digital circuitry. Various adjustments can be made to obtain
optimum performance for all processing units.
9.10.1 Receiver circuit block diagram

Figure 10 shows the block diagram of the receiver circuit. The receiving process can be
broken down in to several steps. Quadrature demodulation of the 13.56 MHz carrier signal
is performed. To achieve the optimum performance, automatic Q-clock calibration is
recommended (see Section 9.10.2.1 on page 31).
The demodulated signal is amplified by an adjustable amplifier. A correlation circuit
calculates the degree of similarity between the expected and the received signal. The
BitPhase register enables correlation interval position alignment with the received signal’s
bit grid. In the evaluation and digitizer circuitry, the valid bits are detected and the digital
results are sent to the FIFO buffer. Several tuning steps are possible for this circuit.
The signal can be observed on its way through the receiver as shown in Figure 10. One
signal at a time can be routed to pin AUX using the T estAnaSelect register as described in
Section 15.2.2 on page 96.
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9.10.2 Receiver operation

In general, the default settings programmed in the StartUp initialization file are suitable for
use with the MFRC500 to MIFARE card data communication. However, in some
environments specific user settings will achieve better performance.
9.10.2.1 Automatic Q-clock calibration

The quadrature demodulation concept of the receiver generates a phase signal (I-clock)
and a 90 phase-shifted quadrature signal (Q-clock). To achieve the optimum
demodulator performance, the Q-clock and the I-clock must be phase-shifted by 90. After
the reset phase, a calibration procedure is automatically performed.
Automatic calibration can be set-up to execute at the end of each Transceive command if
bit ClkQCalib= logic 0. Setting bit ClkQCalib= logic 1 disables all automatic calibrations
except after the reset sequence. Automatic calibration can also be triggered by the
software when bit ClkQCalib has a logic 0 to logic 1 transition.
Remark: The duration of the automatic Q-clock calibration is 65 oscillator periods or

approximately 4.8 s.
The ClockQControl register’s ClkQDelay[4:0] value is proportional to the phase-shift
between the Q-clock and the I-clock. The ClkQ180Deg status flag bit is set when the
phase-shift between the Q-clock and the I-clock is greater than 180.
Remark:
The StartUp configuration file enables automatic Q-clock calibration after a reset If bit ClkQCalib= logic 1, automatic calibration is not performed. Leaving this bit set to
logic 1 can be used to permanently disable automatic calibration. It is possible to write data to the ClkQDelay[4:0] bits using the microprocessor. The
aim could be to disable automatic calibration and set the delay using the software.
Configuring the delay value using the software requires bit ClkQCalib to have been
previously set to logic 1 and a time interval of at least 4.8 s has elapsed. Each delay
value must be written with bit ClkQCalib set to logic 1. If bit ClkQCalib is logic 0, the
configured delay value is overwritten by the next automatic calibration interval.
9.10.2.2 Amplifier

The demodulated signal must be amplified by the variable amplifier to achieve the best
performance. The gain of the amplifiers can be adjusted using the RxControl1 register
Gain[1:0] bits; see Table 23.
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9.10.2.3 Correlation circuitry

The correlation circuitry calculates the degree of matching between the received and an
expected signal. The output is a measure of the amplitude of the expected signal in the
received signal. This is done for both, the Q and I-channels. The correlator provides two
outputs for each of the two input channels, resulting in a total of four output signals.
The correlation circuitry needs the phase information for the incoming card signal for
optimum performance. This information is defined for the microprocessor using the
BitPhase register. This value defines the phase relationship between the transmitter and
receiver clock in multiples of the BitPhase time (tBitPhase)=1/13.56MHz.
9.10.2.4 Evaluation and digitizer circuitry

The correlation results are evaluated for each bit-half of the Manchester encoded signal.
The evaluation and digitizer circuit decides from the signal strengths of both bit-halves, if
the current bit is valid If the bit is valid, its value is identified If the bit is not valid, it is checked to identify if it contains a bit-collision
Select the following levels for optimal using RxThreshold register bits: MinLevel[3:0]: defines the minimum signal strength of the stronger bit-halve’s signal
which is considered valid. CollLevel[3:0]: defines the minimum signal strength relative to the amplitude of the
stronger half-bit that has to be exceeded by the weaker half-bit of the Manchester
encoded signal to generate a bit-collision. If the signal’s strength is below this value,
logic 1 and logic 0 can be determined unequivocally.
After data transmission, the card is not allowed to send its response before a preset time
period which is called the frame guard time in the ISO/IEC 14443 standard. The length of
this time period is set using the RxWait register’s RxWait[7:0] bits. The RxWait register
defines when the receiver is switched on after data transmission to the card in multiples of
one bit duration.
If bit RcvClkSelI is set to logic 1, the I-clock is used to clock the correlator and evaluation
circuits. If bit RcvClkSelI is set to logic 0, the Q-clock is used.
Remark: It is recommended to use the Q-clock.
9.11 Serial signal switch

The MFRC500 comprises two main blocks:
Table 23. Gain factors for the internal amplifier

See Table 78 “RxControl1 register bit descriptions” on page 55 for additional information. 20 24 31 35
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amplification circuitry
The interface between these two blocks can be configured so that the interface signals
are routed to pins MFIN and MFOUT. This makes it possible to connect the analog part of
one MFRC500 to the digital part of another device.
9.11.1 Serial signal switch block diagram

Figure 12 shows the serial signal switches. Three different switches are implemented in
the serial signal switch enabling the MFRC500 to be used in different configurations.
The serial signal switch can also be used to check the transmitted and received data
during the design-in phase or for test purposes. Section 15.2.1 on page 94 describes the
analog test signals and measurements at the serial signal switch.
Remark: The SLR400 uses pin name SIGOUT for pin MFOUT. The MFRC500

functionality includes the test modes for the SLRC400 using pin MFOUT.
Section 9.11.2, Section 9.11.2.1 and Section 9.11.2.2 describe the relevant registers and
settings used to configure and control the serial signal switch.
9.11.2 Serial signal switch registers
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The TxControl register ModulatorSource[1:0] bits define the signal used to modulate the
transmitted 13.56 MHz energy carrier. The modulated signal drives pins TX1 and TX2.
The MFOUTSelect register MFOUTSelect[2:0] bits select the output signal which is to be
routed to pin MFOUT.
Remark: To use the MFOUTSelect[2:0] bits, the T
estDigiSelect register SignalToMFOUT
bit must be logic 0.
9.11.2.1 Active antenna concept

The MFRC500 analog and digital circuitry is accessed using pins MFIN and MFOUT.
Table 27 lists the required settings.
Table 24. DecoderSource[1:0] values

See Table 88 on page 57 for additional information. 00 constant 0 01 output of the analog part. This is the default configuration 10 direct connection to pin MFIN; expects an 847.5 kHz subcarrier
signal modulated by a Manchester encoded signal 11 direct connection to pin MFIN; expects a Manchester encoded
signal
Table 25. ModulatorSource[1:0] values

See Table 88 on page 57 for additional information. 00 constant 0 (energy carrier off on pins TX1 and TX2) 01 constant 1 (continuous energy carrier on pins TX1 and TX2) 10 modulation signal (envelope) from the internal encoder. This is the
default configuration. 11 direct connection to MFIN; expects a Miller pulse coded signal
Table 26. MFOUTSelect[2:0] values

See Table 102 on page 60 for additional information. 000 constant LOW 001 constant HIGH 010 modulation signal (envelope) from the internal encoder 011 serial data stream to be transmitted; the same as for
MFOUTSelect[2:0]= 010 but not encoded by the selected pulse
encoder 100 output signal of the receiver circuit; card modulation signal
regenerated and delayed 101 output signal of the subcarrier demodulator; Manchester coded card
signal
6110 reserved
7111 reserved
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[1] The number column refers to the value in the number column of Table 24, Table 25 and Table 26.
Two MFRC500 devices configured as described in Table 27 can be connected to each
other using pins MFOUT and MFIN.
9.11.2.2 Driving both RF parts

It is possible to connect both passive and active antennas to a single IC. The passive
antenna pins TX1, TX2 and RX are connected using the appropriate filter and matching
circuit. At the same time an active antenna is connected to pins MFOUT and MFIN. In this
configuration, two RF parts can be driven, one after another, by one microprocessor.
9.12 MIFARE authentication and Crypto1

The security algorithm used in the MIFARE products is called Crypto1. It is based on a
proprietary stream cipher with a 48-bit key length. To access data on MIFARE cards,
knowledge of the key format is needed. The correct key must be available in the
MFRC500 to enable successful card authentication and access to the card’s data stored
in the EEPROM.
After a card is selected as defined in ISO/IEC 14443 A standard, the user can continue
with the MIFARE protocol. It is mandatory that the card authentication is performed.
Crypto1 authentication is a 3-pass authentication which is automatically performed when
the Authent1 and Authent2 commands are executed (see Section 11.6.3 on page 82 and
Section 11.6.4 on page 82).
During the card authentication procedure, the security algorithm is initialized. After a
successful authentication, communication with the MIFARE card is encrypted.
9.12.1 Crypto1 key handling

On execution of the authentication command, the MFRC500 reads the key from the key
buffer. The key is always read from the key buffer and ensures Crypto1 authentication
commands do not require addressing of a key. The user must ensure the correct key is
prepared in the key buffer before triggering card authentication.
The key buffer can be loaded from: the EEPROM using the LoadKeyE2 command (see Section 11.6.1 on page 81) the microprocessor’s FIFO buffer using the LoadKey command (see Section 11.6.2
on page 81). This is shown in Figure 13.
Table 27. Register settings to enable use of the analog circuitry
Analog circuitry settings

ModulatorSource 3 Miller pulse encoded MFIN
MFOUTSelect 4 Manchester encoded with subcarrier MFOUT
DecoderSource X - -
Digital circuitry settings

ModulatorSource X - -
MFOUTSelect 2 Miller pulse encoded MFOUT
DecoderSource 2 Manchester encoded with subcarrier MFIN
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9.12.2 Authentication procedure

The Crypto1 security algorithm enables authentication of MIFARE cards. To obtain valid
authentication, the correct key has to be available in the key buffer of the MFRC500. This
can be ensured as follows: Load the internal key buffer by using the LoadKeyE2 (see Section 11.6.1 on page 81)
or the LoadKey (see Section 11.6.2 on page 81) commands. Start the Authent1 command (see Section 11.6.3 on page 82). When finished, check
the error flags to obtain the command execution status. Start the Authent2 command (see Section 11.6.4 on page 82). When finished, check
the error flags and bit Crypto1On to obtain the command execution status.
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The "Original" MIFARE reader solution
10. MFRC500 registers
10.1 Register addressing modes

Three methods can be used to operate the MFRC500: initiating functions and controlling data by executing commands configuring the functional operation using a set of configuration bits monitoring the state of the MFRC500 by reading status flags
The commands, configuration bits and flags are accessed using the microprocessor
interface. The MFRC500 can internally address 64 registers using six address lines.
10.1.1 Page registers

The MFRC500 register set is segmented into eight pages contain eight registers each. A
Page register can always be addressed, irrespective of which page is currently selected.
10.1.2 Dedicated address bus

When using the MFRC500 with the dedicated address bus, the microprocessor defines
three address lines using address pins A0, A1 and A2. This enables addressing within a
page. To switch between registers in different pages a paging mechanism needs to be
used.
Table 28 shows how the register address is assembled.
10.1.3 Multiplexed address bus

The microprocessor may define all six address lines at once using the MFRC500 with a
multiplexed address bus. In this case either the paging mechanism or linear addressing
can be used.
Table 29 shows how the register address is assembled.
Table 28. Dedicated address bus: assembling the register address
PageSelect2 PageSelect1 PageSelect0 A2 A1 A0
Table 29. Multiplexed address bus: assembling the register address

Paging mode 1 PageSelect2 PageSelect1 PageSelect0 AD2 AD1 AD0
Linear
addressing AD5 AD4 AD3 AD2 AD1 AD0
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The "Original" MIFARE reader solution
10.2 Register bit behavior

Bits and flags for different registers behave differently, depending on their functions. In
principle, bits with same behavior are grouped in common registers. Table 30 describes
the function of the Access column in the register tables. Table 30. Behavior and designation of register bits
R/W read and write These bits can be read and written by the microprocessor.
Since they are only used for control, their content is not
influenced by internal state machines.
Example: TimerReload register may be read and written by

the microprocessor. It will also be read by internal state
machines but never changed by them. dynamic These bits can be read and written by the microprocessor. Nevertheless, they may also be written automatically by
internal state machines.
Example: the Command register changes its value
automatically after the execution of the command. read only These registers hold flags which have a value determined by
internal states only.
Example: the ErrorFlag register cannot be written externally
but shows internal states. write only These registers are used for control only. They may be written
by the microprocessor but cannot be read. Reading these
registers returns an undefined value.
Example: The TestAnaSelect register is used to determine the

signal on pin AUX however, it is not possible to read its
content.
0, 1 or x generic value Where applicable, the values 0 and 1 indicate the expected
logic value for a given bit. Where X is used, any logic value can
be entered
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
10.3 Register overview
Table 31. MFRC500 register overview
Page 0: Command and status

00h Page selects the page register Table 33 on page43
01h Command starts and stops command execution Table 35 on page44
02h FIFOData input and output of 64-byte FIFO buffer Table 37 on page44
03h PrimaryStatus receiver and transmitter and FIFO buffer status flags Table 39 on page45
04h FIFOLength number of bytes buffered in the FIFO buffer Table 41 on page46
05h SecondaryStatus secondary status flags Table 43 on page46
06h InterruptEn enable and disable interrupt request control bits Table 45 on page47
07h InterruptRq interrupt request flags Table 47 on page47
Page 1: Control and status

08h Page selects the page register Table 33 on page43
09h Control control flags for timer unit, power saving etc Table 49 on page48
0Ah ErrorFlag show the error status of the last command executed Table 51 on page49
0Bh CollPos bit position of the first bit-collision detected on the RF interface Table 53 on page50
0Ch TimerValue value of the timer Table 55 on page50
0Dh CRCResultLSB LSB of the CRC coprocessor register Table 57 on page50
0Eh CRCResultMSB MSB of the CRC coprocessor register Table 59 on page51
0Fh BitFraming adjustments for bit oriented frames Table 61 on page51
Page 2: Transmitter and coder control

10h Page selects the page register Table 33 on page43
11h TxControl controls the operation of the antenna driver pins TX1 and TX2 Table 63 on page52
12h CwConductance selects the conductance of the antenna driver pins TX1 and TX2 Table 65 on page53
13h PreSet13 do not change these values Table 67 on page53
14h PreSet14 do not change these values Table 69 on page53
15h ModWidth selects the modulation pulse width Table 71 on page54
16h PreSet16 do not change these values Table 73 on page54
17h PreSet17 do not change these values Table 75 on page54
Page 3: Receiver and decoder control
Page selects the page register Table 33 on page43 RxControl1 controls receiver behavior Table 77 on page55 DecoderControl controls decoder behavior Table 79 on page55 BitPhase selects the bit-phase between transmitter and receiver clock Table 81 on page56 RxThreshold selects thresholds for the bit decoder Table 83 on page56 PreSet1D do not change these values Table 85 on page56
1Eh RxControl2 controls decoder and defines the receiver input source Table 87 on page57
1Fh ClockQControl clock control for the 90 phase-shifted Q-channel clock Table 89 on page57
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The "Original" MIFARE reader solution
Page 4: RF Timing and channel redundancy

20h Page selects the page register Table 33 on page43
21h RxWait selects the interval after transmission before the receiver starts Table 91 on page58
22h ChannelRedundancy selects the method and mode used to check data integrity on
the RF channel
Table 93 on page58
23h CRCPresetLSB preset LSB value for the CRC register Table 95 on page59
24h CRCPresetMSB preset MSB value for the CRC register Table 97 on page59
25h PreSet25 do not change these values Table 99 on page59
26h MFOUTSelect selects internal signal applied to pin MFOUT, includes the MSB
of value TimeSlotPeriod; see Table 101 on page60
Table 101 on page60
27h PreSet27 do not change these values Table 103 on page60
Page 5: FIFO, timer and IRQ pin configuration

28h Page selects the page register Table 33 on page43
29h FIFOLevel defines the FIFO buffer overflow and underflow warning levels Table 41 on page46
2Ah TimerClock selects the timer clock divider Table 107 on page61
2Bh TimerControl selects the timer start and stop conditions Table 109 on page62
2Ch TimerReload defines the timer preset value Table 111 on page62
2Dh IRQPinConfig configures pin IRQ output stage Table 113 on page63
2Eh PreSet2E do not change these values Table 115 on page63
2Fh PreSet2F do not change these values Table 116 on page63
Page 6: reserved registers

30h Page selects the page register Table 33 on page43
31h reserved reserved Table 117 on page63
32h reserved reserved
33h reserved reserved
34h reserved reserved
35h reserved reserved
36h reserved reserved
37h reserved reserved
Page 7: Test control

38h Page selects the page register Table 33 on page43
39h reserved reserved Table 118 on page64
3Ah TestAnaSelect selects analog test mode Table 119 on page64
3Bh reserved reserved Table 121 on page65
3Ch reserved reserved Table 122 on page65
3Dh TestDigiSelect selects digital test mode Table 123 on page65
3Eh reserved reserved Table 125 on page66
3Fh reserved reserved
Table 31. MFRC500 register overview …continued
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The "Original" MIFARE reader solution
10.4 MFRC500 register flags overview
Table 32. MFRC500 register flags overview
AccessErr ErrorFlag 5 0Ah
BitPhase[7:0] BitPhase 7 to 0 1Bh
ClkQ180Deg ClockQControl 7 1Fh
ClkQCalib ClockQControl 6 1Fh
ClkQDelay[4:0] ClockQControl 4 to 0 1Fh
CollErr ErrorFlag 0 0Ah
CollLevel[3:0] RxThreshold 3 to 0 1Ch
CollPos[7:0] CollPos 7 to 0 0Bh
Command[5:0] Command 5 to 0 01h
CRC3309 ChannelRedundancy 5 22h
CRC8 ChannelRedundancy 4 22h
CRCErr ErrorFlag 3 0Ah
CRCPresetLSB[7:0] CRCPresetLSB 7 to 0 23h
CRCPresetMSB[7:0] CRCPresetMSB 7 to 0 24h
CRCReady SecondaryStatus 5 05h
CRCResultMSB[7:0] CRCResultMSB 7 to 0 0Eh
CRCResultLSB[7:0] CRCResultLSB 7 to 0 0Dh
Crypto1On Control 3 09h
DecoderSource[1:0] RxControl2 1 to 0 1Eh
E2Ready SecondaryStatus 6 05h
Err PrimaryStatus 2 03h
FIFOData[7:0] FIFOData 7 to 0 02h
FIFOLength[6:0] FIFOLength 6 to 0 04h
FIFOOvfl ErrorFlag 4 0Ah
FlushFIFO Control 0 09h
FramingErr ErrorFlag 2 0Ah
Gain[1:0] RxControl1 1 to 0 19h
GsCfgCW[5:0] CwConductance 5 to 0 12h
HiAlert PrimaryStatus 1 03h
HiAlertIEn InterruptEn 1 06h
HiAlertIRq InterruptRq 1 07h
IdleIEn InterruptEn 2 06h
IdleIRq InterruptRq 2 07h
IFDetectBusy Command 7 01h
IRq PrimaryStatus 3 03h
IRQInv IRQPinConfig 1 2Dh
IRQPushPull IRQPinConfig 0 2Dh
KeyErr ErrorFlag 6 0Ah
LoAlert PrimaryStatus 0 03h
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LoAlertIEn InterruptEn 0 06h
LoAlertIRq InterruptRq 0 07h
MFOUTSelect[2:0] MFOUTSelect 2 to 0 26h
MinLevel[3:0] RxThreshold 7 to 4 1Ch
ModemState[2:0] PrimaryStatus 6 to 4 03h
ModulatorSource[1:0] TxControl 6 to 5 11h
ModWidth[7:0] ModWidth 7 to 0 15h
PageSelect[2:0] Page 2 to 0 00h, 08h, 10h, 18h, 20h, 28h, 30h
and 38h
ParityEn ChannelRedundancy 0 22h
ParityErr ErrorFlag 1 0Ah
ParityOdd ChannelRedundancy 1 22h
PowerDown Control 4 09h
RcvClkSelI RxControl2 7 1Eh
RxAlign[2:0] BitFraming 6 to 4 0Fh
RxAutoPD RxControl2 6 1Eh
RxCRCEn ChannelRedundancy 3 22h
RxIEn InterruptEn 3 06h
RxIRq InterruptRq 3 07h
RxLastBits[2:0] SecondaryStatus 2 to 0 05h
RxMultiple DecoderControl 6 1Ah
RxWait[7:0] RxWait 7 to 0 21h
SetIEn InterruptEn 7 06h
SetIRq InterruptRq 7 07h
SignalToMFOUT TestDigiSelect 7 3Dh
StandBy Control 5 09h
TAutoRestart TimerClock 5 2Ah
TestAnaOutSel[4:0] TestAnaSelect 3 to 0 3Ah
TestDigiSignalSel[6:0] TestDigiSelect 6 to 0 3Dh
TimerIEn InterruptEn 5 06h
TimerIRq InterruptRq 5 07h
TimerValue[7:0] TimerValue 7 to 0 0Ch
TPreScaler[4:0] TimerClock 4 to 0 2Ah
TReloadValue[7:0] TimerReload 7 to 0 2Ch
TRunning SecondaryStatus 7 05h
TStartTxBegin TimerControl 0 2Bh
TStartTxEnd TimerControl 1 2Bh
TStartNow Control 1 09h
TStopRxBegin TimerControl 2 2Bh
TStopRxEnd TimerControl 3 2Bh
TStopNow Control 2 09h
Table 32. MFRC500 register flags overview …continued
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
10.5 Register descriptions
10.5.1 Page 0: Command and status
10.5.1.1 Page register

Selects the page register.
TX1RFEn TxControl 0 11h
TX2Cw TxControl 3 11h
TX2Inv TxControl 3 11h
TX2RFEn TxControl 1 11h
TxCRCEn ChannelRedundancy 2 22h
TxIEn InterruptEn 4 06h
TxIRq InterruptRq 4 07h
TxLastBits[2:0] BitFraming 2 to 0 0Fh
UsePageSelect Page 7 00h, 08h, 10h, 18h, 20h, 28h, 30h
and 38h
WaterLevel[5:0] FIFOLevel 5 to 0 29h
ZeroAfterColl DecoderControl 5 1Ah
Table 32. MFRC500 register flags overview …continued
Table 33. Page register (address: 00h, 08h, 10h, 18h, 20h, 28h, 30h, 38h)
reset value: 1000 0000b, 80h bit allocation
Table 34. Page register bit descriptions
UsePageSelect1 the value of PageSelect[2:0] is used as the register address
A5, A4, and A3. The LSBs of the register address are defined using the address pins or the internal address latch,
respectively. the complete content of the internal address latch defines
the register address. The address pins are used as described in Table 5 on page8.
6 to 3 0000 - reserved
2 to 0 PageSelect[2:0]- when UsePageSelect= logic 1, the value of PageSelect is
used to specify the register page (A5, A4 and A3 of the
register address)
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
10.5.1.2 Command register

Starts and stops the command execution.
10.5.1.3 FIFOData register

Input and output of the 64 byte FIFO buffer.
Table 35. Command register (address: 01h) reset value: x000 0000b, x0h bit allocation
Table 36. Command register bit descriptions
IFDetectBusy shows the status of interface detection logic interface detection finished successfully interface detection ongoing 0 - reserved
5 to 0 Command[5:0]- activates a command based on the Command code.
Reading this register shows which command is being
executed.
Table 37. FIFOData register (address: 02h) reset value: xxxx xxxxb, xxh bit allocation
Table 38. FIFOData register bit descriptions

7 to 0 FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer. The FIFO
buffer acts as a parallel in to parallel out converter for all data streams.
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
10.5.1.4 PrimaryStatus register

Bits relating to receiver, transmitter and FIFO buffer status flags.
Table 39. PrimaryStatus register (address: 03h) reset value: 0000 0101b, 05h bit allocation
Table 40. PrimaryStatus register bit descriptions
0 - reserved
6 to 4 ModemState[2:0] shows the state of the transmitter and receiver
state machines:
000 Idle neither the transmitter or receiver are operating;
neither of them are started or have input data
001 TxSOF transmit start of frame pattern
010 TxData transmit data from the FIFO buffer (or
redundancy CRC check bits)
011 TxEOF transmit End Of Frame (EOF) pattern
100 GoToRx1 intermediate state 1; receiver starts
GoToRx2 intermediate state 2; receiver finishes
101 PrepareRx waiting until the RxWait register time period
expires
110 AwaitingRx receiver activated; waiting for an input signal on
pin RX
111 Receiving receiving data IRq - shows any interrupt source requesting attention
based on the InterruptEn register flag settings Err 1 any error flag in the ErrorFlag register is set HiAlert 1 the alert level for the number of bytes in the FIFO buffer (FIFOLength[6:0]) is:
otherwise value= logic0
Example:
FIFOLength = 60, WaterLevel = 4 then
HiAlert= logic1
FIFOLength = 59, WaterLevel = 4 then
HiAlert= logic0 LoAlert 1 the alert level for number of bytes in the FIFO
buffer (FIFOLength[6:0]) is:
value= logic0
Example:
FIFOLength = 4, WaterLevel = 4 then
LoAlert= logic1
FIFOLength = 5, WaterLevel = 4 then
LoAlert= logic0
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10.5.1.5 FIFOLength register

Number of bytes in the FIFO buffer.
10.5.1.6 SecondaryStatus register

Various secondary status flags.
Table 41. FIFOLength register (address: 04h) reset value: 0000 0000b, 00h bit allocation
Table 42. FIFOLength bit descriptions
0 reserved
6 to 0 FIFOLength[6:0] gives the number of bytes stored in the FIFO buffer. Writing
increments the FIFOLength register value while reading decrements
the FIFOLength register value
Table 43. SecondaryStatus register (address: 05h) reset value: 01100 000b, 60h bit
allocation
Table 44. SecondaryStatus register bit descriptions
TRunning 1 the timer unit is running and the counter decrements the
TimerValue register on the next timer clock cycle the timer unit is not running E2Ready 1 EEPROM programming is finished EEPROM programming is ongoing CRCReady 1 CRC calculation is finished CRC calculation is ongoing
4 to 3 00 - reserved
2 to 0 RxLastBits[2:0]- shows the number of valid bits in the last received byte. If zero,
the whole byte is valid
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The "Original" MIFARE reader solution
10.5.1.7 InterruptEn register

Control bits to enable and disable passing of interrupt requests.
[1] This bit can only be set or cleared using bit SetIEn.
10.5.1.8 InterruptRq register

Interrupt request flags.
Table 45. InterruptEn register (address: 06h) reset value: 0000 0000b, 00h bit allocation
Table 46. InterruptEn register bit descriptions
SetIEn 1 indicates that the marked bits in the InterruptEn register are set clears the marked bits 0 - reserved TimerIEn - sends the TimerIRq timer interrupt request to pin IRQ[1] TxIEn - sends the TxIRq transmitter interrupt request to pin IRQ[1] RxIEn - sends the RxIRq receiver interrupt request to pin IRQ[1] IdleIEn - sends the IdleIRq idle interrupt request to pin IRQ[1] HiAlertIEn- sends the HiAlertIRq high alert interrupt request to pin IRQ[1] LoAlertIEn- sends the LoAlertIRq low alert interrupt request to pin IRQ[1]
Table 47. InterruptRq register (address: 07h) reset value: 0000 0000b, 00h bit allocation
Table 48. InterruptRq register bit descriptions
SetIRq 1 sets the marked bits in the InterruptRq register clears the marked bits in the InterruptRq register - reserved TimerIRq 1 timer decrements the TimerValue register to zero timer decrements are still greater than zero TxIRq 1 TxIRq is set to logic 1 if one of the following events occurs:
Transceive command; all data transmitted
Authent1 and Authent2 commands; all data transmitted
WriteE2 command; all data is programmed
CalcCRC command; all data is processed when not acted on by Transceive, Authent1, Authent2, WriteE2 or
CalcCRC commands RxIRq 1 the receiver terminates reception still ongoing
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The "Original" MIFARE reader solution

[1] PrimaryStatus register Bit HiAlertIRq stores this event and it can only be reset using bit SetIRq.
10.5.2 Page 1: Control and status
10.5.2.1 Page register

Selects the page register; see Section 10.5.1.1 “Page register” on page 43.
10.5.2.2 Control register

Various control flags, for timer, power saving, etc.
[1] This bit can only be set to logic 1 by successful execution of the Authent2 command
[2] Reading this bit always returns logic 0 IdleIRq 1 command terminates correctly. For example; when the Command
register changes its value from any command to the Idle command.
If an unknown command is started the IdleIRq bit is set.
Microprocessor start-up of the Idle command does not set the
IdleIRq bit. IdleIRq= logic 0 in all other instances HiAlertIRq 1 PrimaryStatus register HiAlert bit is set[1] PrimaryStatus register HiAlert bit is not set LoAlertIRq 1 PrimaryStatus register LoAlert bit is set[1] PrimaryStatus register LoAlert bit is not set
Table 48. InterruptRq register bit descriptions …continued
Table 49. Control register (address: 09h) reset value: 0000 0000b, 00h bit allocation
Table 50. Control register bit descriptions

7 to 6 00 - reserved StandBy 1 activates Standby mode. The current consuming blocks are
switched off but the clock keeps running PowerDown 1 activates Power-down mode. The current consuming blocks
are switched off including the clock Crypto1On 1 Crypto1 unit is switched on and all data communication with
the card is encrypted[1] Crypto1 unit is switched off. All data communication with the
card is unencrypted (plain) TStopNow 1 immediately stops the timer[2] TStartNow 1 immediately starts the timer[2] FlushFIFO 1 immediately clears the internal FIFO buffer’s read and write
pointer, the FIFOLength[6:0] bits are set to logic 0 and the
FIFOOvfl flag[2]
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The "Original" MIFARE reader solution
10.5.2.3 ErrorFlag register

Error flags show the error status of the last executed command.
Table 51. ErrorFlag register (address: 0Ah) reset value: 0100 0000b, 40h bit allocation
Table 52. ErrorFlag register bit descriptions
0 - reserved KeyErr 1 set when the LoadKeyE2 or LoadKey command recognize that the
input data is not encoded based on the key format definition set when the LoadKeyE2 or the LoadKey command starts AccessErr 1 set when the access rights to the EEPROM are violated set when an EEPROM related command starts FIFOOvfl 1 set when the microprocessor or MFRC500 internal state machine
(e.g. receiver) tries to write data to the FIFO buffer when it is full CRCErr 1 set when RxCRCEn is set and the CRC fails automatically set during the PrepareRx state in the receiver start
phase FramingErr 1 set when the SOF is incorrect automatically set during the PrepareRx state in the receiver start
phase ParityErr 1 set when the parity check fails automatically set during the PrepareRx state in the receiver start
phase CollErr 1 set when a bit-collision is detected automatically set during the PrepareRx state in the receiver start
phase
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
10.5.2.4 CollPos register

Bit position of the first bit-collision detected on the RF interface.
10.5.2.5 TimerValue register

Value of the timer.
10.5.2.6 CRCResultLSB register

LSB of the CRC coprocessor register.
Table 53. CollPos register (address: 0Bh) reset value: 0000 0000b, 00h bit allocation
Table 54. CollPos register bit descriptions

7 to 0 CollPos[7:0] this register shows the bit position of the first detected collision in a
received frame.
Example:
00h indicates a bit collision in the start bit
01h indicates a bit collision in the 1 st bit
08h indicates a bit collision in the 8 th bit
Table 55. TimerValue register (address: 0Ch) reset value: xxxx xxxxb, xxh bit allocation
Table 56. TimerValue register bit descriptions

7 to 0 TimerValue[7:0] this register shows the timer counter value
Table 57. CRCResultLSB register (address: 0Dh) reset value: xxxx xxxxb, xxh bit
allocation
Table 58. CRCResultLSB register bit descriptions

7 to 0 CRCResultLSB[7:0] gives the CRC register’s least significant byte value; only valid if
CRCReady= logic1
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
10.5.2.7 CRCResultMSB register

MSB of the CRC coprocessor register.
10.5.2.8 BitFraming register

Adjustments for bit oriented frames.
Table 59. CRCResultMSB register (address: 0Eh) reset value: xxxx xxxxb, xxh bit
allocation
Table 60. CRCResultMSB register bit descriptions

7 to 0 CRCResultMSB[7:0] gives the CRC register’s most significant byte value; only valid if
CRCReady= logic1.
The register’s value is undefined for 8-bit CRC calculation.
Table 61. BitFraming register (address: 0Fh) reset value: 0000 0000b, 00h bit allocation
Table 62. BitFraming register bit descriptions
- reserved
6 to 4 RxAlign[2:0] defines the bit position in the FIFO buffer for the first bit received
and stored. Additional received bits are stored in the next
subsequent bit positions. After reception, RxAlign[2:0] is
automatically cleared. For example:
000 the LSB of the received bit is stored in bit position 0 and the
second received bit is stored in bit position 1
001 the LSB of the received bit is stored in bit position 1, the
second received bit is stored in bit position 2
111 the LSB of the received bit is stored in bit position 7, the
second received bit is stored in the next byte in bit position 0 - reserved
2 to 0 TxLastBits[2:0]- defines the number of bits of the last byte that shall be
transmitted. 000 indicates that all bits of the last byte will be
transmitted. TxLastBits[2:0] is automatically cleared after
transmission.
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
10.5.3 Page 2: Transmitter and control
10.5.3.1 Page register

Selects the page register; see Section 10.5.1.1 “Page register” on page 43.
10.5.3.2 TxControl register

Controls the logical behavior of the antenna pins TX1 and TX2.
Table 63. TxControl register (address: 11h) reset value: 0101 1000b, 58h bit allocation
Table 64. TxControl register bit descriptions
0 - this value must not be changed
6 to 5 ModulatorSource[1:0] selects the source for the modulator input: modulator input is LOW modulator input is HIGH modulator input is the internal encoder modulator input is pin MFIN 1 - this value must not be changed TX2Inv 1 delivers an inverted 13.56 MHz energy carrier output
signal on pin TX2 TX2Cw 1 delivers a continuously unmodulated 13.56 MHz
energy carrier output signal on pin TX2 enables modulation of the 13.56 MHz energy carrier TX2RFEn 1 the output signal on pin TX2 is the 13.56 MHz energy
carrier modulated by the transmission data TX2 is driven at a constant output level TX1RFEn 1 the output signal on pin TX1 is the 13.56 MHz energy
carrier modulated by the transmission data TX1 is driven at a constant output level
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
10.5.3.3 CwConductance register

Selects the conductance of the antenna driver pins TX1 and TX2.
See Section 9.9.3.1 for detailed information about GsCfgCW[5:0].
10.5.3.4 PreSet13 register

These bit settings must not be changed.
10.5.3.5 PreSet14 register

These bit settings must not be changed.
Table 65. CwConductance register (address: 12h) reset value: 0011 1111b, 3Fh bit
allocation
Table 66. CwConductance register bit descriptions

7 to 6 00 0 these values must not be changed
5 to 0 GsCfgCW[5:0]- defines the conductance register value for the output driver.
This can be used to regulate the output power/current consumption and operating distance.
Table 67. PreSet13 register (address: 13h) reset value: 0011 1111b, 3Fh bit allocation
Table 68. PreSet13 register bit descriptions

7 to 6 00 0 these values must not be changed
5 to 0 11111 - these values must not be changed
Table 69. PreSet14 register (address: 14h) reset value: 0001 1001b, 19h bit allocation
Table 70. PreSet14 register bit descriptions

7 to 5 000 0 these values must not be changed
4 to 3 11 1 these values must not be changed
2 to 1 00 0 these values must not be changed 1 1 these values must not be changed
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
10.5.3.6 ModWidth register

Selects the pulse-modulation width.
10.5.3.7 PreSet16 register

These bit settings must not be changed.
10.5.3.8 PreSet17 register

These bit settings must not be changed.
Table 71. ModWidth register (address: 15h) reset value: 0001 0011b, 13h bit allocation
Table 72. ModWidth register bit descriptions

7 to 0 ModWidth[7:0] defines the width of the modulation pulse based on
tmod =2(ModWidth + 1)/fclk
Table 73. PreSet16 register (address: 16h) reset value: 0000 0000b, 00h bit allocation
Table 74. PreSet16 register bit descriptions

7 to 0 00000000 0 these values must not be changed
Table 75. PreSet17 register (address: 17h) reset value: 0000 0000b, 00h bit allocation
Table 76. PreSet17 register bit descriptions

7 to 0 00000000 0 these values must not be changed
NXP Semiconductors MFRC500
The "Original" MIFARE reader solution
10.5.4 Page 3: Receiver and decoder control
10.5.4.1 Page register

Selects the page register; see Section 10.5.1.1 “Page register” on page 43.
10.5.4.2 RxControl1 register

Controls receiver operation.
10.5.4.3 DecoderControl register

Controls decoder operation.
Table 77. RxControl1 register (address: 19h) reset value: 0111 0011b, 73h bit allocation
Table 78. RxControl1 register bit descriptions
0 0 these values must not be changed
6 to 4 111 1 these values must not be changed
3 to 2 00 0 these values must not be changed
1 to 0 Gain[1:0] defines the receiver’s signal voltage gain factor 20 dB gain factor 24 dB gain factor 31 dB gain factor 35 dB gain factor
Table 79. DecoderControl register (address: 1Ah) reset value: 0000 1000b, 08h bit
allocation
Table 80. DecoderControl register bit descriptions
0 - this value must not be changed RxMultiple 0 after receiving one frame, the receiver is deactivated enables reception of more than one frame ZeroAfterColl 1 any bits received after a bit-collision are masked to zero. This
helps to resolve the anti-collision procedure as defined in
ISO/IEC 14443A 0 0 this value must not be changed 1 1 this value must not be changed
2 to 0 000 0 these values must not be changed
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