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MCM67B618AFN10MOTN/a220avai64K x 18 Bit BurstRAM Synchronous Fast Static RAM
MCM67B618AFN12MOTOROLAN/a8avai64K x 18 Bit BurstRAM Synchronous Fast Static RAM
MCM67B618AFN9MOTOROLAN/a527avai64K x 18 Bit BurstRAM Synchronous Fast Static RAM
MCM67B618AFN9MOTN/a115avai64K x 18 Bit BurstRAM Synchronous Fast Static RAM
MCM67B618AFN-9 |MCM67B618AFN9MOTON/a8avai64K x 18 Bit BurstRAM Synchronous Fast Static RAM


MCM67B618AFN9 ,64K x 18 Bit BurstRAM Synchronous Fast Static RAMMAXIMUM RATINGS (Voltages Referenced to V = 0 V)SSThis device contains circuitry to protect theRati ..
MCM67B618AFN9 ,64K x 18 Bit BurstRAM Synchronous Fast Static RAM**Order this documentSEMICONDUCTOR TECHNICAL DATAby MCM67B618A/DMCM67B618A64K x 18 Bit BurstRAMSyn ..
MCM67B618AFN-9 ,64K x 18 Bit BurstRAM Synchronous Fast Static RAMBLOCK DIAGRAM (See Note)ADVBURST LOGICINTERNALADDRESSQ0A0′KA01664K × 18MEMORYQ1 A1′ARRAYCLR A1ADSCA ..
MCM67C618AFN7 ,64K x 18 Bit BurstRAM Synchronous Fast Static RAM**Order this documentSEMICONDUCTOR TECHNICAL DATAby MCM67C618A/DMCM67C618A64K x 18 Bit BurstRAMSyn ..
MCM67H518FN9 ,32K x 18 Bit BurstRAM Synchronous Fast Static RAMMAXIMUM RATINGS (Voltages Referenced to V = 0 V)SSThis device contains circuitry to protect theRati ..
MCM67M618AFN10 ,64K x 18 Bit BurstRAM Synchronous Fast Static RAMMAXIMUM RATINGS (Voltages Referenced to V = 0 V)SSThis device contains circuitry to protect theRati ..
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MCM67B618AFN10-MCM67B618AFN12-MCM67B618AFN9-MCM67B618AFN-9
64K x 18 Bit BurstRAM Synchronous Fast Static RAM
64K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Self–Timed Write

The MCM67B618A is a 1,179,648 bit synchronous fast static random access
memory designed to provide a burstable, high–performance, secondary cache
for the i486 and Pentium microprocessors. It is organized as 65,536 words
of 18 bits. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive capability outputs onto a single monolithic circuit for re-
duced parts count implementation of cache data RAM applications. Synchro-
nous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated func-
tions for greater reliability.
Addresses (A0 – A15), data inputs (D0 – D17), and all control signals
except output enable (G) are clock (K) controlled through positive–edge–
triggered noninverting registers.
Bursts can be initiated with either address status processor (ADSP) or
address status cache controller (ADSC) input pins. Subsequent burst
addresses can be generated internally by the MCM67B618A (burst
sequence imitates that of the i486 and Pentium) and controlled by the burst
address advance (ADV) input pin. The following pages provide more de-
tailed information on burst controls.
Write cycles are internally self–timed and are initiated by the rising edge
of the clock (K) input. This feature eliminates complex off–chip write pulse
generation and provides increased flexibility for incoming signals.
Dual write enables (LW and UW) are provided to allow individually write-
able bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls
DQ9 – DQ17 (the upper bits).
This device is ideally suited for systems that require wide data bus
widths and cache memory. See Figure 2 for applications information. Single 5 V ± 5% Power Supply Fast Access Times: 9/10/12 ns Max Byte Writeable via Dual Write Enables Internal Input Registers (Address, Data, Control) Internally Self–Timed Write Cycle ADSP, ADSC, and ADV Burst Control Pins Asynchronous Output Enable Controlled Three–State Outputs Common Data Inputs and Data Outputs 3.3 V I/O Compatible High Board Density 52–Lead PLCC Package
BurstRAM is a trademark of Motorola, Inc.
i486 and Pentium are trademarks of Intel Corp.DQ9
VCC
DQ8
DQ6
DQ7
VSS
DQ4
DQ5
DQ2
DQ3
VSS
VCC
DQ0
DQ1
VCC
VSS
VSS
VCC
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17A7EUW K A8A9A10LW G
A15A3A2
A13A14 A12 A0
ADVADSCADSP
All power supply and ground pins must be
connected for proper operation of the device.
PIN ASSIGNMENTS
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