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MCM63P733ATQ100MOTOROLAN/a2avai128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P733ATQ117MOTN/a4avai128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P733ATQ133MOTN/a869avai128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
MCM63P733ATQ90MOTN/a20avai128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM


MCM63P733ATQ133 ,128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM**Order this documentby MCM63P733A/DSEMICONDUCTOR TECHNICAL DATAMCM63P733AAdvance Information128K x ..
MCM63P733ATQ90 ,128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM**Order this documentby MCM63P733A/DSEMICONDUCTOR TECHNICAL DATAMCM63P733AAdvance Information128K x ..
MCM63Z736TQ100 ,128K x 36 and 256K x 18 Bit Pipelined ZBT RAM Synchronous Fast Static RAM
MCM63Z736TQ133 ,128K x 36 and 256K x 18 Bit Pipelined ZBT RAM Synchronous Fast Static RAM
MCM63Z737TQ11 ,128K x 36 and 256K x 18 Bit Flow-Through ZBT RAM Synchronous Fast Static RAM
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MCM63P733ATQ100-MCM63P733ATQ117-MCM63P733ATQ133-MCM63P733ATQ90
128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
Advance Information
128K x 32 Bit Pipelined
BurstRAM Synchronous
Fast Static RAM

The MCM63P733A is a 4M–bit synchronous fast static RAM designed to pro-
vide a burstable, high performance, secondary cache for the PowerPC and
other high performance microprocessors. It is organized as 128K words of 32
bits each, fabricated with high performance silicon gate CMOS technology.
This device integrates input registers, an output register, a 2–bit address
counter, and high speed SRAM onto a single monolithic circuit for reduced
parts count in cache data RAM applications. Synchronous design allows pre-
cise cycle control with the use of an external clock (K). CMOS circuitry reduces
the overall power consumption of the integrated functions for greater reliability.
Addresses (SA), data inputs (DQx), and all control signals except output
enable (G) and Linear Burst Order (LBO) are clock (K) controlled through
positive–edge–triggered noninverting registers.
Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burst
addresses can be generated internally by the MCM63P733A (burst sequence
operates in linear or interleaved mode dependent upon state of LBO) and con-
trolled by the burst address advance (ADV) input pin.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
Synchronous byte write (SBx), synchronous global write (SGW), and synchro-
nous write enable (SW) are provided to allow writes to either individual bytes or
to all bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controls
DQa, SBb controls DQb, etc. Individual bytes are written if the selected byte
writes SBx are asserted with SW. All bytes are written if either SGW is asserted
or if all SBx and SW are asserted.
For read cycles, pipelined SRAMs output data is temporarily stored by an
edge–triggered output register and then released to the output buffers at the next
rising edge of clock (K).
The MCM63P733A operates from a 3.3 V core power supply and all outputs
operate on a 2.5 V or 3.3 V power supply. All inputs and outputs are JEDEC
standard JESD8–5 compatible. MCM63P733A–133 = 4 ns Access/7.5 ns Cycle (133 MHz)
MCM63P733A–117 = 4.2 ns Access/8.5 ns Cycle (117 MHz)
MCM63P733A–100 = 4.5 ns Access/10 ns Cycle (100 MHz)
MCM63P733A–90 = 5 ns Access/11 ns Cycle (90 MHz) 3.3 V + 10%/– 5% Core, Power Supply, 2.5 V or 3.3 V I/O Supply ADSP, ADSC, and ADV Burst Control Pins Selectable Burst Sequencing Order (Linear/Interleaved) Internally Self–Timed Write Cycle Byte Write and Global Write Control Single–Cycle Deselect Sleep Mode (ZZ) 100–Pin TQFP Package
PowerPC is a trademark of IBM Corp.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
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