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MC88921
LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature
Order this document
from Logic Marketing-
SEMICONDUCTOR TECHNICAL DATA# "### !
The MC88921 Clock Driver utilizes phase–locked loop technology to
lock its low skew outputs’ frequency and phase onto an input reference
clock. It is designed to provide clock distribution for CISC microprocessor
or single processor RISC systems.
The PLL allows the high current, low skew outputs to lock onto a single
clock input and distribute it with essentially zero delay to multiple
locations on a board. The PLL also allows the MC88921 to multiply a low
frequency input clock and distribute it locally at a higher (2X) system
frequency. 2X_Q Output Meets All Requirements of the 20, 25 and 33MHz 68040
Microprocessor PCLK Input Specifications 60 and 66MHz Output to Drive the Pentium Microprocessor Four Outputs (Q0–Q3) With Output–Output Skew <500ps and Six
Outputs Total (Q0–Q3, 2X_Q) With <1ns Skew Each Being Phase and
Frequency Locked to the SYNC Input The Phase Variation From Part–to–Part Between SYNC and the ‘Q’
Outputs Is Less Than 600ps (Derived From the TPD Specification,
Which Defines the Part–to–Part Skew) SYNC Input Frequency Range From 5MHZ to 2X_Q FMax/4 Additional Outputs Available at 2X the System ‘Q’ Frequency All Outputs Have ±36mA Drive (Equal High and Low) CMOS Levels.
Can Drive Either CMOS or TTL Inputs. All Inputs Are TTL–Level
Compatible Test Mode Pin (PLL_EN) Provided for Low Frequency Testing Special Power–Down Mode With 2X_Q, Q0, and Q1 Being Reset (With
MR), and Other Outputs Remain Running. 2X_Q, Q0 and Q1 Are
Guaranteed to Be in Lock 3 Clock Cycles After MR Is Negated
Four ‘Q’ outputs (Q0–Q3) are provided with less than 500ps skew between their rising edges. A 2X_Q output runs at twice the
‘Q’ output frequency. The 2X_Q output is ideal for 68040 systems which require a 2X processor clock input. The 2X_Q output
meets the tight duty cycle spec of the 20, 25 and 33MHz 68040. The 66MHz 2X_Q output can also be used for driving the clock
input of the Pentium Microprocessor while providing multiple 33MHz outputs to drive the support and bus logic. The FBSEL pin
allows the user to internally feedback either the Q or the Q/2 frequency providing a 1x or 2x multiplication factor of the reference
input.
In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the
88921 in a static ‘test mode’. In this mode there is no frequency limitation on the input clock, which is necessary for a low
frequency board test environment.
A lock indicator output (LOCK) will go HIGH when the loop is in steady state phase and frequency lock. The output will go LOW
if phase–lock is lost or when the PLL_EN pin is LOW. The lock output will go HIGH no later than 10ms after the 88921 sees a sync
signal and full 5.0V VCC.
