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MC88915TFN100 180pcs , PLCC,LOW SKEW CMOS PLL CLOCK DRIVER
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MC88915TFN100 N/a 180
MC88915TFN100 from MOT, Motorola 383pcs , PLCC28,LOW SKEW CMOS PLL CLOCK DRIVER
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block diagram onpage 2). In most applications FREQ_SEL should be held high (÷1). If a low frequency reference clock input is used, holdingFREQ_SEL low (÷2) will allow the VCO to run in its optimal range (>20MHz and >40MHz for the TFN133 version).In normal phase–locked operation the PLL_EN pin is held high. Pulling the PLL_EN pin low disables the VCO and puts the 88915in a static “test mode”. In this mode there is no frequency limitation on the input clock, which is necessary for a low frequency boardtest environment. The second SYNC input can be used as a test clock input to further simplify board–level testing (see detaileddescription on page 11).Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0–Q4, Q5 and Q/2 into a high impedance state (3–state). After theOE/RST pin goes back high Q0–Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNCinput. Assuming PLL_EN is low, the outputs will remain reset until the 88915 sees a SYNC input pulse.A lock indicator output (LOCK) will go high when the loop is in steady–state phase and frequency lock. The LOCK output will golow if phase–lock is lost or when the PLL_EN pin is low. The LOCK output will go high no later than 10ms after the 88915 sees aSYNC signal and full 5V V .CCFeatures• Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input• The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPDspecification, which defines the part–to–part skew)• Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available• Input frequency range from 5MHz – 2X_Q FMAX spec. (10MHz – 2X_Q FMAX for the TFN133 version)• Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180° phase shift) output available• All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputsare TTL–level compatible. ±88mA I /I specifications guarantee 50Ω transmission line switching on the incident edgeOL OH• Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.All outputs can go into high impedance (3–state) for board test purposes• Lock Indicator (LOCK) accuracy indicates a phase–locked stateYield Surface Modeling and YSM are trademarks of Motorola, Inc.1/97REV 4 Motorola, Inc. 1997 1MC88915TFN55/70/100/133/160Pinout: 28–Lead PLCC (Top View)OE/RST V Q5 GND Q4 V 2X_QCC CC43 2 1 28 27 26FEEDBACK 5 25 Q/2REF_SEL6 24 GNDSYNC[0]7 23 Q3V (AN) 8 22 VCC CCRC19 21 Q2GND(AN) 10 20 GNDSYNC[1]11 19 LOCK12 13 14 15 16 17 18FREQ_SEL GND Q0 V Q1 GND PLL_ENCCFN SUFFIXPLASTIC PLCCCASE 776–02PIN SUMMARYPin Name Num I/O Function1SYNC[0] Input Reference clock input1SYNC[1] Input Reference clock input1REF_SEL Input Chooses reference between sync[0] & Sync[1]1FREQ_SEL Input Doubles VCO Internal Frequency (low)1FEEDBACK Input Feedback input to phase detector 1RC1 Input Input for external RC network5Q(0–4) Clock output (locked to sync)Output1Q5 Output Inverse of clock output12x_Q 2 x clock output (Q) frequency (synchronous) Output1Q/2 Output Clock output(Q) frequency ÷ 2 (synchronous)1LOCK Indicates phase lock has been achieved (high when locked)Output1OE/RST Output Enable/Asynchronous reset (active low)Input1PLL_EN Disables phase–lock for low freq. testingInput11V ,GND Power and ground pins (note pins 8, 10 are CC“analog” supply pins for internal PLL only)MOTOROLA 2 TIMING SOLUTIONSBR1333 — Rev 6MC88915TFN55/70/100/133/160LOCKFEEDBACKSYNC (0)VOLTAGE0PHASE/FREQ.CHARGE PUMP/LOOP M CONTROLLEDFILTERDETECTORUOSCILLATORXSYNC (1)1EXTERNAL REC NETWORK(RC1 Pin)REF_SEL2x_Q0 1PLL_ENMUXQ0DQ(÷1)CPQ1RMU(÷2)XDIVIDE0BY TWOQ1DQCPRFREQ_SELOE/RSTQ2DQCPRQ3DQCPRQ4DQCPRQ5DQCPRQ/2DQCPRMC88915T **SEMICONDUCTOR TECHNICAL DATA*"’ ’ * * "** *#*&*#$* %*%** * *!* **( *#$*"!$ **The MC88915T Clock Driver utilizes phase–locked loop technology to*lock its low skew outputs’ frequency and phase onto an input referenceclock. It is designed to provide clock distribution for high performancePC’s and workstations. For a 3.3V version, see the MC88LV915T datasheet.The PLL allows the high current, low skew outputs to lock onto a singleLOW SKEW CMOSclock input and distribute it with essentially zero delay to multiplecomponents on a board. The PLL also allows the MC88915T to multiply aPLL CLOCK DRIVERlow frequency input clock and distribute it locally at a higher (2X) systemfrequency. Multiple 88915’s can lock onto a single reference clock, whichis ideal for applications when a central system clock must be distributedsynchronously to multiple boards (see Figure 7).Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180°phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q”frequency.The VCO is designed to run optimally between 20 MHz and the 2X_Q F specification. The wiring diagrams in Figure 5 detailmaxthe different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the“Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the **SEMICONDUCTOR TECHNICAL DATA*"’ ’ * * "** *#*&*#$* %*%** * *!* **( *#$*"!$ **The MC88915T Clock Driver utilizes phase–locked loop technology to*lock its low skew outputs’ frequency and phase onto an input referenceclock. It is designed to provide clock distribution for high performancePC’s and workstations. For a 3.3V version, see the MC88LV915T datasheet.The PLL allows the high current, low skew outputs to lock onto a singleLOW SKEW CMOSclock input and distribute it with essentially zero delay to multiplecomponents on a board. The PLL also allows the MC88915T to multiply aPLL CLOCK DRIVERlow frequency input clock and distribute it locally at a higher (2X) systemfrequency. Multiple 88915’s can lock onto a single reference clock, whichis ideal for applications when a central system clock must be distributedsynchronously to multiple boards (see Figure 7).Five “Q” outputs (Q0–Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180°phase shift) from the “Q” outputs. The 2X_Q output runs at twice the “Q” output frequency, while the Q/2 runs at 1/2 the “Q”frequency.The VCO is designed to run optimally between 20 MHz and the 2X_Q F specification. The wiring diagrams in Figure 5 detailmaxthe different feedback configurations which create specific input/output frequency relationships. Possible frequency ratios of the“Q” outputs to the SYNC input are 2:1, 1:1, and 1:2.The FREQ_SEL pin provides one bit programmable divide–by in the feedback path of the PLL. It selects between divide–by–1and divide–by–2 of the VCO before its signal reaches the internal clock distribution section of the chip (see the Features• Five Outputs (Q0–Q4) with Output–Output Skew < 500 ps each being phase and frequency locked to the SYNC input• The phase variation from part–to–part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPDspecification, which defines the part–to–part skew)• Input/Output phase–locked frequency ratios of 1:2, 1:1, and 2:1 are available• Input frequency range from 5MHz – 2X_Q FMAX spec. (10MHz – 2X_Q FMAX for the TFN133 version)• Additional outputs available at 2X and +2 the system “Q” frequency. Also a Q (180° phase shift) output available• All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputsare TTL–level compatible. ±88mA I /I specifications guarantee 50Ω transmission line switching on the incident edgeOL OH• Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes.All outputs can go into high impedance (3–state) for board test purposes• Lock Indicator (LOCK) accuracy indicates a phase–locked stateYield Surface Modeling and YSM are trademarks of Motorola, Inc.1/97REV 4 Motorola, Inc. 1997 1MC88915TFN55/70/100/133/160Pinout: 28–Lead PLCC (Top View)OE/RST V Q5 GND Q4 V 2X_QCC CC43 2 1 28 27 26FEEDBACK 5 25 Q/2REF_SEL6 24 GNDSYNC[0]7 23 Q3V (AN) 8 22 VCC CCRC19 21 Q2GND(AN) 10 20 GNDSYNC[1]11 19 LOCK12 13 14 15 16 17 18FREQ_SEL GND Q0 V Q1 GND PLL_ENCCFN SUFFIXPLASTIC PLCCCASE 776–02PIN SUMMARYPin Name Num I/O Function1SYNC[0] Input Reference clock input1SYNC[1] Input Reference clock input1REF_SEL Input Chooses reference between sync[0] & Sync[1]1FREQ_SEL Input Doubles VCO Internal Frequency (low)1FEEDBACK Input Feedback input to phase detector 1RC1 Input Input for external RC network5Q(0–4) Clock output (locked to sync)Output1Q5 Output Inverse of clock output12x_Q 2 x clock output (Q) frequency (synchronous) Output1Q/2 Output Clock output(Q) frequency ÷ 2 (synchronous)1LOCK Indicates phase lock has been achieved (high when locked)Output1OE/RST Output Enable/Asynchronous reset (active low)Input1PLL_EN Disables phase–lock for low freq. testingInput11V ,GND Power and ground pins (note pins 8, 10 are CC“analog” supply pins for internal PLL only)MOTOROLA 2 TIMING SOLUTIONSBR1333 — Rev 6MC88915TFN55/70/100/133/160LOCKFEEDBACKSYNC (0)VOLTAGE0PHASE/FREQ.CHARGE PUMP/LOOP M CONTROLLEDFILTERDETECTORUOSCILLATORXSYNC (1)1EXTERNAL REC NETWORK(RC1 Pin)REF_SEL2x_Q0 1PLL_ENMUXQ0DQ(÷1)CPQ1RMU(÷2)XDIVIDE0BY TWOQ1DQCPRFREQ_SELOE/RSTQ2DQCPRQ3DQCPRQ4DQCPRQ5DQCPRQ/2DQCPRMC88915T

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