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MC74VHCT573ADWMOTN/a114avaiOctal D-Type Latch with 3-State Output
MC74VHCT573ADWR2ONN/a7000avaiOctal D-Type Latch with 3-State Output


MC74VHCT573ADWR2 ,Octal D-Type Latch with 3-State OutputON SemiconductorOctal D-Type LatchMC74VHCT573Awith 3-State OutputThe MC74VHCT573A is an advanced h ..
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MC74VHCT573ADW-MC74VHCT573ADWR2
Octal D-Type Latch with 3-State Output
Octal D-T ype Latch
with 3-State Output
The MC74VHCT573A is an advanced high speed CMOS octal latch
with 3–state output fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
This 8–bit D–type latch is controlled by a latch enable input and an
output enable input. When the output enable input is high, the eight
outputs are in a high impedance state.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3V to 5.0V , because it has
full 5V CMOS level output swings.
The VHCT573A input and output (when disabled) structures
provide protection when voltages between 0V and 5.5V are applied,
regardless of the supply voltage. These input and output structures
help prevent device destruction caused by supply voltage –
input/output voltage mismatch, battery backup, hot insertion, etc. High Speed: tPD = 7.7ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Designed for 4.5V to 5.5V Operating Range Low Noise: VOLP = 1.6V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 234 FETs or 58.5 Equivalent Gates
Figure 1. Logic Diagram

DATA
INPUTS
NONINVERTING
OUTPUTS
Figure 2. Pin Assignment

GND
VCC
FUNCTION TABLE
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