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MC74VHC1GT86-MC74VHC1GT86DFT1-MC74VHC1GT86DFT2-MC74VHC1GT86DTT1 Fast Delivery,Good Price
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MC74VHC1GT86MOTON/a27avaiSingle 2 Input Exclusive OR Gate, TTL Level
MC74VHC1GT86DFT1ONN/a1500avaiSingle 2 Input Exclusive OR Gate, TTL Level
MC74VHC1GT86DFT2ONN/a19500avai2-Input Exclusive OR Gate/CMOS Logic Level Shifter
MC74VHC1GT86DTT1ONN/a3000avai2-Input Exclusive OR Gate/CMOS Logic Level Shifter


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MC74VHC1GT86-MC74VHC1GT86DFT1-MC74VHC1GT86DFT2-MC74VHC1GT86DTT1
Single 2 Input Exclusive OR Gate, TTL Level
MC74VHC1GT86
2-Input Exclusive OR Gate /
CMOS Logic Level Shifter
with LSTTL–Compatible Inputs

The MC74VHC1GT86 is an advanced high speed CMOS 2–input
Exclusive OR gate fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar Schottky
TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The device input is compatible with TTL–type input thresholds and the
output has a full 5 V CMOS level output swing. The input protection
circuitry on this device allows overvoltage tolerance on the input,
allowing the device to be used as a logic–level translator from 3.0 V
CMOS logic to 5.0V CMOS Logic or from 1.8 V CMOS logic to 3.0 V
CMOS Logic while operating at the high–voltage power supply.
The MC74VHC1GT86 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT86 to be used to interface 5 V circuits to 3 V
circuits. The output structures also provide protection when VCC = 0 V.
These input and output structures help prevent device destruction caused
by supply voltage – input/output voltage mismatch, battery backup, hot
insertion, etc. High Speed: tPD = 4.8 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 1 μA (Max) at TA = 25°C TTL–Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V CMOS–Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 83; Equivalent Gates = 16
Figure 1. Pinout (T
op View)
IN A OUT Y
IN B
VCCIN B
IN A
OUT YGND
Figure 2. Logic Symbol
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