MC74VHC1G86DFT1 ,Single 2 Input Exclusive OR Gate2NORMALIZED FAILURE RATET = 130°CJT = 120°CJT = 110° CJT = 100°CJT= 90J °CT= 80J °CMC74VHC1G86DC
MC74VHC1G86DFT1G ,Single 2 Input Exclusive OR GateMAXIMUM RATINGSSymbol Parameter Value UnitV DC Supply Voltage 0.5 to 7.0 VCCV DC Input Voltage −0 ..
MC74VHC1G86DFT1G ,Single 2 Input Exclusive OR GateMC74VHC1G86Single 2-InputExclusive OR GateThe MC74VHC1G86 is an advanced high speed CMOS 2−inputExc ..
MC74VHC1G86DFT2 ,Single 2 Input Exclusive OR GateELECTRICAL CHARACTERISTICS C = 50 pF, Input t = t = 3.0 nsload r fÎÎT = 25°C T ≤ 85°C −55 ≤ T ≤ 125 ..
MC74VHC1G86DFT2G ,Single 2 Input Exclusive OR GateMaximum Ratings are those values beyond which damage to the device may occur. Exposure to these con ..
MC74VHC1G86DTT1 ,Single 2 Input Exclusive OR Gateoutput which provides high noise immunity and stable output.The MC74VHC1G86 input structure provide ..
MDP1603-101G ,Thick Film Resistor Networks, Dual-In-Line, Molded DIP, 01, 03, 05 SchematicsELECTRICAL SPECIFICATIONSMODEL/ SCHEMATIC RESISTOR RESISTANCE STANDARD TEMPERATURE TCR WEIGHTNO. OF ..
MDP1645 ,Dual Inline Package, Molded DIP, Rugged, Molded Case Construction, Highly Stable, Automatic Insert Compatible, Available in Tube Pack, Reduces Assembly Costs For Technical Questions, contact: ff2aresistors Document Number: 3151244 Revision 25-Oct-00MDP 164 ..
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MC74VHC1G86-MC74VHC1G86DFT1-MC74VHC1G86DFT1G-MC74VHC1G86DFT2-MC74VHC1G86DFT2G-MC74VHC1G86DTT1
Single 2 Input Exclusive OR Gate
MC74VHC1G86
Single 2-Input
Exclusive OR Gate
The MC74VHC1G86 is an advanced high speed CMOS 2−input
Exclusive OR gate fabricated with silicon gate CMOS technology.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The MC74VHC1G86 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1G86 to be used to interface 5 V circuits to 3 V
circuits. High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V Low Power Dissipation: ICC = 1 �A (Max) at TA = 25°C Power Down Protection Provided on Inputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 54
Figure 1. Pinout (T op View)
VCCIN B
IN A
OUT YGND
IN A
IN B OUT Y
Figure 2. Logic Symbol
