MC74VHC157MEL ,Quad 2-Channel Multiplexer**SEMICONDUCTOR TECHNICAL DATA* The MC74VHC157 is an advanced high speed CMOS quad 2–channelmultip ..
MC74VHC157MEL ,Quad 2-Channel MultiplexerMAXIMUM RATINGS*Symbol Parameter Value UnitThis device contains protectionÎÎÎcircuitry to guard aga ..
MC74VHC1G00 ,Single 2-Input NAND Gatevoltages up to 7.0 V are applied, regardless of the supply voltage. Thisallows the MC74VHC1G00 to b ..
MC74VHC1G00 ,Single 2-Input NAND GateMaximum Ratings are those values beyond which damage to the device may occur. Exposure to these con ..
MC74VHC1G00DFT1 ,2-Input NAND Gateoutput which provides high noise immunity and stable output.The MC74VHC1G00 input structure provide ..
MC74VHC1G00DFT2 ,2-Input NAND Gate3MC74VHC1G00VCCOUTPUTVINPUTCCA or B50%CGND L*t tPLH PHLY *Includes all probe and jig capacitance.50 ..
MDP1603-101G ,Thick Film Resistor Networks, Dual-In-Line, Molded DIP, 01, 03, 05 SchematicsELECTRICAL SPECIFICATIONSMODEL/ SCHEMATIC RESISTOR RESISTANCE STANDARD TEMPERATURE TCR WEIGHTNO. OF ..
MDP1645 ,Dual Inline Package, Molded DIP, Rugged, Molded Case Construction, Highly Stable, Automatic Insert Compatible, Available in Tube Pack, Reduces Assembly Costs For Technical Questions, contact: ff2aresistors Document Number: 3151244 Revision 25-Oct-00MDP 164 ..
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MDS35-800 ,DIODE / SCR MODULEapplications,ISOTOP®using phase controlled bridges, such as soft-startcircuits, welding equipment, ..
MDS50-1200 ,DIODE / SCR MODULEFEATURES:Symbol Value UnitI50-70-85 AT(RMS)V /V800 and 1200 VDRM RRMI 50 and 100 mAGTDESCRIPTIONPac ..
MDS50-800 ,DIODE / SCR MODULEMDS35/50 /80SeriesDIODE / SCR MODULEMAIN
MC74VHC157MEL
Quad 2-Channel Multiplexer
SEMICONDUCTOR TECHNICAL DATA -
The MC74VHC157 is an advanced high speed CMOS quad 2–channel
multiplexer fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
It consists of four 2–input digital multiplexers with common select (S) and
enable (E) inputs. When E is held High, selection of data is inhibited and all
the outputs go Low.
The select decoding determines whether the A or B inputs get routed to
the corresponding Y outputs.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems. High Speed: tPD = 4.1ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 4μA (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.5V Operating Range Low Noise: VOLP = 0.8V (Max) Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V Chip Complexity: 82 FETs or 20 Equivalent Gates
EXPANDED LOGIC DIAGRAMDATA
OUTPUTS
NIBBLE
INPUTS
FUNCTION TABLE
