MC74HC541AF-L1 ,Octal 3-State Non-Inverting Buffer/Line Driver/Line ReceiverMAXIMUM RATINGS*ÎÎÎÎÎÎ Symbol ParameterÎÎÎÎÎ ValueÎÎÎ UnitThis device contains protectioncircuitry ..
MC74HC541AN ,Octal 3-State Non-Inverting Buffer/Line Driver/Line ReceiverMAXIMUM RATINGS (Note 1)Symbol Parameter Value UnitV DC Supply Voltage 0.5 to 7.0 VCCV DC Input V ..
MC74HC563N ,Octal 3-State Inverting Transparent Latch
MC74HC563N ,Octal 3-State Inverting Transparent Latch
MC74HC564AN ,Octal 3-State Inverting D Flip-FlopELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaran ..
MC74HC564N ,Octal 3-State Inverting D Flip-FlopMAXIMUM RATINGS*ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MD54-0003TR ,MMIC Medium Level Mixer 1700
MD54-0003TR ,MMIC Medium Level Mixer 1700
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0007TR ,Low Cost MMIC Mixer, 2.1
MC74HC541ADTEL-MC74HC541AFL1-MC74HC541AF-L1
Octal 3-State Non-Inverting Buffer/Line Driver/Line Receiver
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High–Performance Silicon–Gate CMOSThe MC74HC541A is identical in pinout to the LS541. The device
inputs are compatible with Standard CMOS outputs. External pullup
resistors make them compatible with LSTTL outputs.
The HC541A is an octal non–inverting buffer/line driver/line
receiver designed to be used with 3–state memory address drivers,
clock drivers, and other bus–oriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
active–low output enables.
The HC541A is similar in function to the HC540A, which has
inverting outputs. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating V oltage Range: 2 to 6V Low Input Current: 1μA High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 134 FETs or 33.5 Equivalent GatesY1A1Y2A2Y3A3Y4A4Y5A5Y6A6Y7A7Y8A8
OE1OE2
Output
Enables
Data
Inputs
Non–Inverting
Outputs
PIN 10 = GND
LOGIC DIAGRAM
Pinout: 20–Lead Packages (Top View)VCC
OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
http://
MARKING
DIAGRAMS = Assembly Location = Wafer Lot = Year = Work Week
SOIC WIDE–20
DW SUFFIX
CASE 751D
PDIP–20
N SUFFIX
CASE 738
ORDERING INFORMATION
FUNCTION TABLEZ = High Impedance
X = Don’t Care
