MC74HC540ADTR2 ,Octal 3-State Inverter Buffer/Line Driver/Line Receiverhttp://onsemi.com3MC74HC540ADC CHARACTERISTICS (Voltages Referenced to GND)Guaranteed LimitV VCC CC ..
MC74HC540ADWR2 ,Octal 3-State Inverter Buffer/Line Driver/Line ReceiverMAXIMUM RATINGS (Note 1.)Symbol Parameter Value UnitV DC Supply Voltage 0.5 to 7.0 VCCV DC Input ..
MC74HC540ADWR2 ,Octal 3-State Inverter Buffer/Line Driver/Line Receiverfeatures inputsand outputs on opposite sides of the package and two ANDed20MC74HC540ANactive–low ou ..
MC74HC540AF ,Octal 3-State Inverter Buffer/Line Driver/Line Receiverhttp://onsemi.com3MC74HC540ADC CHARACTERISTICS (Voltages Referenced to GND)Guaranteed LimitV VCC CC ..
MC74HC540AF ,Octal 3-State Inverter Buffer/Line Driver/Line Receiverfeatures inputsand outputs on opposite sides of the package and two ANDed20MC74HC540ANactive–low ou ..
MC74HC540AFEL ,Octal 3-State Inverter Buffer/Line Driver/Line ReceiverMAXIMUM RATINGS (Note 1.)Symbol Parameter Value UnitV DC Supply Voltage 0.5 to 7.0 VCCV DC Input ..
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MC74HC540A-MC74HC540ADTR2-MC74HC540ADWR2-MC74HC540AF-MC74HC540AFEL-MC74HC540AN
Octal 3-State Inverter Buffer/Line Driver/Line Receiver
MC74HC540A
Octal 3-State Inverting
Buffer/Line Driver/Line
Receiver
High–Performance Silicon–Gate CMOSThe MC74HC540A is identical in pinout to the LS540. The device
inputs are compatible with Standard CMOS outputs. External pull–up
resistors make them compatible with LSTTL outputs.
The HC540A is an octal inverting buffer/line driver/line receiver
designed to be used with 3–state memory address drivers, clock
drivers, and other bus–oriented systems. This device features inputs
and outputs on opposite sides of the package and two ANDed
active–low output enables.
The HC540A is similar in function to the HC541A, which has
noninverting outputs. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 �A High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 124 FETs or 31 Equivalent Gates
Figure 1. Pinout: 20–Lead Packages (Top View)VCC
OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND
FUNCTION TABLEZ = High Impedance
X = Don’t Care
ORDERING INFORMATION
http://
MARKING
DIAGRAMS
TSSOP–20
DT SUFFIX
CASE 948E
SO–20
DW SUFFIX
CASE 751D
PDIP–20
N SUFFIX
CASE 783 = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW= Work Week
