MC74HC4060 ,14-Stage Binary Ripple Counter With Oscillator2MC74HC4060ADC CHARACTERISTICS (Voltages Referenced to GND)Guaranteed LimitV VCC CCV VSymbol Symbol ..
MC74HC4060A ,14-Stage Binary Ripple Counter with OscillatorMaximum Ratings are those values beyond which damage to the device may occur.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC4060AD ,14-Stage Binary Ripple Counter With Oscillator
MC74HC4060ADR2G , 14−Stage Binary Ripple Counter With Oscillator
MC74HC4060ADT ,14-Stage Binary Ripple Counter with Oscillatorhttp://onsemi.com3MC74HC4060AAC CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns) - continuedL r fGua ..
MC74HC4060ADTR2G , 14−Stage Binary Ripple Counter With Oscillator
MD54-0003TR ,MMIC Medium Level Mixer 1700
MD54-0003TR ,MMIC Medium Level Mixer 1700
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0004TR ,800-1000 MHz, MMIC medium level mixer
MD54-0007TR ,Low Cost MMIC Mixer, 2.1
MC74HC4060
14-Stage Binary Ripple Counter With Oscillator
----
High–Performance Silicon–Gate CMOSThe MC74C4060A is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of 14 master–slave flip–flops and an oscillator
with a frequency that is controlled either by a crystal or by an RC
circuit connected externally. The output of each flip–flop feeds the
next and the frequency at each output is half of that of the preceding
one. The state of the counter advances on the negative–going edge of
the Osc In. The active–high Reset is asynchronous and disables the
oscillator to allow very low power consumption during stand–by
operation.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with Osc Out 2 of the
HC4060A. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating V oltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance With JEDEC Standard No. 7A Requirements Chip Complexity: 390 FETs or 97.5 Equivalent Gates
VCC
Q10 Q8 Q9 Reset Osc In
Osc
Out 1
Osc
Out 2
Q12 Q13 Q14 Q6 Q5 Q7 Q4 GND
Pinout: 16–Lead Plastic Package (Top View)
FUNCTION TABLE
