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MC74HC4040AFEL from MOT, Motorola 85pcs , SOIC-16/5.2mm,Monolithic WFR, Binary Counter
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MC74HC4040AFEL MOT N/a 85
http://onsemi.com2MC74HC4040ADC CHARACTERISTICS (Voltages Referenced to GND)Guaranteed LimitV VCC CCV V –55 to 25°C ≤85°C ≤125°CSymbol Parameter Condition UnitSymbol Parameter Condition UnitV = V or V |I | ≤ 2.4mA 3.0 0.26 0.33 0.40in IH IL out|I | ≤ 4.0mA 4.5 0.26 0.33 0.40out|I | ≤ 5.2mA 6.0 0.26 0.33 0.40outI Maximum Input Leakage Current V = V or GND 6.0 ±0.1 ±1.0 ±1.0 μAin in CCI Maximum Quiescent Supply V = V or GND 6.0 4 40 160 μACC in CCCurrent (per Package) I = 0μAoutNOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book(DL129/D).AC CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)L r fGuaranteed LimitV VCC CCV –55 to 25°C ≤85°C ≤125°CSymbol Parameter Unitf Maximum Clock Frequency (50% Duty Cycle) 2.0 10 9.0 8.0 MHzmax(Figures 1 and 4) 3.0 15 14 124.5 30 28 256.0 50 45 40t , Maximum Propagation Delay, Clock to Q1* 2.0 96 106 115 nsPLHt (Figures 1 and 4) 3.0 63 71 88PHL4.5 31 36 406.0 25 30 35t Maximum Propagation Delay, Reset to Any Q 2.0 45 52 65 nsPHL(Figures 2 and 4) 3.0 30 36 404.5 30 35 406.0 26 32 35t , Maximum Propagation Delay, Qn to Qn+1 2.0 69 80 90 nsPLHt (Figures 3 and 4) 3.0 40 45 50PHL4.5 17 21 286.0 14 15 22t , Maximum Output Transition Time, Any Output 2.0 75 95 110 nsTLHt (Figures 1 and 4) 3.0 27 32 36THL4.5 15 19 226.0 13 15 19C Maximum Input Capacitance 10 10 10 pFinNOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ONSemiconductor High–Speed CMOS Data Book (DL129/D).* For T = 25°C and C = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:A LV = 2.0 V: t = [93.7 + 59.3 (n–1)] ns V = 4.5 V: t = [30.25 + 14.6 (n–1)] nsCC P CC PV = 3.0 V: t = [61.5 + 34.4 (n–1)] ns V = 6.0V: t = [24.4 + 12 (n–1)] nsCC P CC PTypical @ 25°C, V = 5.0 VCC31C Power Dissipation Capacitance (Per Package)* pFPD2* Used to determine the no–load dynamic power consumption: P = C V f + I V . For load considerations, see Chapter 2 of theD PD CC CC CCON Semiconductor High–Speed CMOS Data Book (DL129/D).

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