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MC74HC4024D-MC74HC4024N
7-Stage Binary Ripple Counter
SEMICONDUCTOR TECHNICAL DATA -
High–Performance Silicon–Gate CMOSThe MC74HC4024 is identical in pinout to the standard CMOS MC14024.
The device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of 7 master–slave flip–flops. The output of each
flip–flop feeds the next and the frequency at each output is half that of the
preceding one. The state of the counter advances on the negative going
edge of the Clock input. Reset is asynchronous and active–high.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and may have to be gated with the Clock of the HC4024 for
some designs. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 206 FETs or 51.5 Equivalent Gates
LOGIC DIAGRAMCLOCK
RESET
PIN 14 = VCC
PIN 7 = GND
PINS 8, 10 AND 13 = NO CONNECTION
