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MC74HC393DR2-MC74HC393FEL-MC74HC393FL1-MC74HC393FR2-MC74HC393N Fast Delivery,Good Price
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Partno Mfg Dc Qty AvailableDescript
MC74HC393DR2MOTN/a900avaiDual 4-Stage Binary Ripple Counter
MC74HC393FELMN/a230avaiDual 4-Stage Binary Ripple Counter
MC74HC393FL1MOTN/a3558avaiDual 4-Stage Binary Ripple Counter
MC74HC393FR2MOTN/a1882avaiDual 4-Stage Binary Ripple Counter
MC74HC393FR2MN/a982avaiDual 4-Stage Binary Ripple Counter
MC74HC393NFAIRCHILDN/a502avaiDual 4-Stage Binary Ripple Counter


MC74HC393FL1 ,Dual 4-Stage Binary Ripple CounterMaximum Ratings are those values beyond which damage to the device may occur. Functional operation ..
MC74HC393FR2 ,Dual 4-Stage Binary Ripple CounterLOGIC DIAGRAMQ1 3 12 RESET baQ2 4 11 Q1a b3, 11Q1Q35 10 Q2ab4, 10Q21, 13BINARYQ4 6 9 Q3CLOCK a b5, ..
MC74HC393FR2 ,Dual 4-Stage Binary Ripple Counter**SEMICONDUCTOR TECHNICAL DATA* * *High–Performance Silicon–Gate CMOSJ SUFFIXCERAMIC PACKAGE14The ..
MC74HC393N ,Dual 4-Stage Binary Ripple CounterELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
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MC74HC393DR2-MC74HC393FEL-MC74HC393FL1-MC74HC393FR2-MC74HC393N
Dual 4-Stage Binary Ripple Counter
SEMICONDUCTOR TECHNICAL DATA- -
High–Performance Silicon–Gate CMOS

The MC54/74HC393 is identical in pinout to the LS393. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device consists of two independent 4–bit binary ripple counters with
parallel outputs from each counter stage. A ÷ 256 counter can be obtained
by cascading the two binary counters.
Internal flip–flops are triggered by high–to–low transitions of the clock
input. Reset for the counters is asynchronous and active–high. State
changes of the Q outputs do not occur simultaneously because of internal
ripple delays. Therefore, decoded output signals are subject to decoding
spikes and should not be used as clocks or as strobes except when gated
with the Clock of the HC393. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 236 FETs or 59 Equivalent Gates
LOGIC DIAGRAM

CLOCK
RESET
1, 13
PIN 14 = VCC
PIN 7 = GND
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