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MC74HC390A-MC74HC390ADR2-MC74HC390ADTR2-MC74HC390AFEL
Dual 4-Stage Binary Ripple Counter with Divide-By-2 and Divide-By-5 Sections
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High–Performance Silicon–Gate CMOSThe MC74HC390A is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4–bit counters, each
composed of a divide–by–two and a divide–by–five section. The
divide–by–two and divide–by–five counters have separate clock
inputs, and can be cascaded to implement various combinations of ÷ 2
and/or ÷ 5 up to a ÷ 100 counter.
Flip–flops internal to the counters are triggered by high–to–low
transitions of the clock input. A separate, asynchronous reset is
provided for each 4–bit counter. State changes of the Q outputs do not
occur simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and should not
be used as clocks or strobes except when gated with the Clock of the
HC390A. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating V oltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No 7A Chip Complexity: 244 FETs or 61 Equivalent Gates
LOGIC DIAGRAM1, 15
PIN 16 = VCC
PIN 8 = GND
CLOCK A
RESET
CLOCK B
FUNCTION TABLE
