MC74HC299N ,8-Bit Bidirectional Universal Shift Register with Parallel I/OELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC299N ,8-Bit Bidirectional Universal Shift Register with Parallel I/Ofeatures a multiplexed parallel input/output data port toDW SUFFIXachieve full 8–bit handling in a ..
MC74HC299N ,8-Bit Bidirectional Universal Shift Register with Parallel I/OMAXIMUM RATINGS*ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
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MC74HC30D ,8-Input NAND GateMaximum Ratings are those values beyond which damage to the device may occur.ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
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MC74HC299N
8-Bit Bidirectional Universal Shift Register with Parallel I/O
SEMICONDUCTOR TECHNICAL DATA!# $!""#! %# ! -
High–Performance Silicon–Gate CMOSThe MC74HC299 is identical in pinout to the LS299. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
The HC299 features a multiplexed parallel input/output data port to
achieve full 8–bit handling in a 20 pin package. Due to the large output drive
capability and the 3–state feature, this device is ideally suited for interface
with bus lines in a bus–oriented system.
Two Mode–Select inputs and two Output Enable inputs are used to
choose the mode of operation as listed in the Function Table. Synchronous
parallel loading is accomplished by taking both Mode–Select lines, S1 and
S2, high. This places the outputs in the high–impedance state, which permits
data applied to the data port to be clocked into the register. Reading out of
the register can be accomplished when the outputs are enabled. The
active–low asynchronous Reset overrides all other inputs. Output Drive Capability: 15 LSTTL Loads for QA through QH
10 LSTTL Loads for QA′ and QH′ Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 398 FETs or 99.5 Equivalent Gates
LOGIC DIAGRAMPG/QG
PE/QE
PC/QC
PA/QA
QA′
QH′
PH/QH
PF/QF
PD/QD
PB/QB
SERIAL
DATA
INPUTS
SA (SHIFT RIGHT)
SH (SHIFT LEFT)
RESET
OE1
OE2
MODE
SELECT
OUTPUT
ENABLES
CLOCK
3–STATE
PARALLEL DATA PORT
(INPUTS/OUTPUTS)
SERIAL DATA
OUTPUTS
PIN 20 = VCC
PIN 10 = GND
