MC74HC11 ,Dual J-K Flip-Flop with Set and ResetELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC11 ,Dual J-K Flip-Flop with Set and ResetELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)L r fÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MC74HC112 ,Dual J-K Flip-Flop with Set and ResetFeatures11 Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and ..
MC74HC112 ,Dual J-K Flip-Flop with Set and ResetELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)L r fGuaranteed Limit 55 toVCC25CV 85 ..
MC74HC112D ,Dual J-K Flip-Flop with Set and Reset**SEMICONDUCTOR TECHNICAL DATA* **High–Performance Silicon–Gate CMOSN SUFFIXPLASTIC PACKAGE16T ..
MC74HC112N ,Dual J-K Flip-Flop with Set and ResetMAXIMUM RATINGS*ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
MCR25M ,Silicon Controlled RectifierELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)JCharacteristic Symbol Min Typ Max Unit ..
MCR25N ,Silicon Controlled RectifierMAXIMUM RATINGS (T = 25°C unless otherwise noted)JRating Symbol Value Unit4(1)Peak Repetitive Off–S ..
MCR265 ,Silicon Controlled RectifiersELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted.)CCharacteristic Symbol Min Typ Max Uni ..
MCR265 ,Silicon Controlled RectifiersMAXIMUM RATINGS (T = 25°C unless otherwise noted)JA KRating Symbol Value Unit(1)Peak Repetitive Off ..
MCR265-10 ,Thyristors**Order this documentSEMICONDUCTOR TECHNICAL DATA by MCR265-2/D*Silicon Controlled Rectifiers. . . ..
MCR265-10 ,ThyristorsMAXIMUM RATINGS (T = 25°C unless otherwise noted.)JRating Symbol Value Unit(1)Peak Repetitive Forwa ..
MC74HC11-MC74HC112D-MC74HC112N
Dual J-K Flip-Flop with Set and Reset
SEMICONDUCTOR TECHNICAL DATA -
High–Performance Silicon–Gate CMOSThe MC74HC112 is identical in pinout to the LS112. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
Each flip–flop is negative–edge clocked and has active–low asynchro-
nous Set and Reset inputs.
The HC112 is identical in function to the HC76, but has a different pinout. Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Similar in Function to the LS112 Except When Set and Reset are Low
Simultaneously Chip Complexity: 100 FETs or 25 Equivalent Gates
LOGIC DIAGRAMRESET 1
CLOCK 1
SET 1
RESET 2
CLOCK 2
SET 2
PIN 16 = VCC
PIN 8 = GND
FUNCTION TABLE Both outputs will remain low as long as Set and
Reset are low, but the output states are unpre-
dictable if Set and Reset go high simultaneously.
