IC Phoenix
 
Home ›  MM117 > MC74F112N,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
MC74F112N Fast Delivery,Good Price
Part Number:
If you need More Quantity or Better Price,Welcom Any inquiry.
We available via phone +865332716050 Email
Partno Mfg Dc Qty AvailableDescript
MC74F112NMOTON/a71avaiDUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
MC74F112NMOTN/a622avaiDUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP


MC74F112N ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
MC74F112N ,DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
MC74F11D ,TRIPLE 3-INPUT AND GATE FAST SCHOTTKY TTL
MC74F1245N ,OCTAL BIDIRECTIONAL TRANSCEIVER WITH 3-STATE INPUTS/OUTPUTS
MC74F1245N ,OCTAL BIDIRECTIONAL TRANSCEIVER WITH 3-STATE INPUTS/OUTPUTS
MC74F125 ,3-STATE QUAD BUFFERSMC54/74F125MC54/74F1263-STATE QUAD BUFFERS• High Impedance NPN Base Inputs for Reduced LoadingQUAD ..
MCP73855T-I/MF , USB Compatible Li-Ion/Li-Polymer Charge Management Controllers
MCP809M3-2.63 ,3-Pin Microprocessor Reset CircuitsPin DescriptionPIN NAME FUNCTION3 GND Ground referenceActive-low output. RESET remains low while V ..
MCP809M3-2.93 ,3-Pin Microprocessor Reset CircuitsPin DescriptionPIN NAME FUNCTION3 GND Ground referenceActive-low output. RESET remains low while V ..
MCP809M3-3.08 ,3-Pin Microprocessor Reset CircuitsPin DescriptionPIN NAME FUNCTION3 GND Ground referenceActive-low output. RESET remains low while V ..
MCP809M3-4.38 ,3-Pin Microprocessor Reset CircuitsFeaturesn Precise monitoring of 3V, 3.3V, and 5V supply voltagesThe MCP809/810 microprocessor super ..
MCP809M3-4.63 ,3-Pin Microprocessor Reset CircuitsPin DescriptionPIN NAME FUNCTION3 GND Ground referenceActive-low output. RESET remains low while V ..


MC74F112N
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP

The MC74F112 contains two independent, high-speed JK flip-flops with Di-
rect Set and Clear inputs. Synchronous state changes are initiated by the fal-
ling edge of the clock. Triggering occurs at a voltage level of the clock and is
not directly related to the transition time. The J and K inputs can change when
the clock is in either state without affecting the flip-flop, provided that they are
in the desired state during the recommended setup and hold times relative to
the falling edge of the clock. A LOW signal on SD or CD prevents clocking and
forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD
force both Q and Q HIGH.
SD1
GNDCP1 J1K1 Q1 Q1 Q2
CONNECTION DIAGRAM

VCC CD1 CD2 CP2 J2 Q2
SD2K2
FUNCTION TABLE (Each Half)

L = LOW Voltage Level
tn = Bit time before clock pulse
tn + 1 = Bit time after clock pulse
ic,good price


TEL:86-533-2716050      FAX:86-533-2716790
   

©2020 IC PHOENIX CO.,LIMITED