MC74AC74D ,Dual D-Type Positive Edge TriggerMAXIMUM RATINGS*Symbol Parameter Value UnitV DC Supply Voltage (Referenced to GND) –0.5 to +7.0 VCC ..
MC74AC74DR2 ,Dual D-Type Positive Edge Triggerpositive edge of the clock pulse. Clock triggering occurs at a voltagelevel of the clock pulse and ..
MC74AC74DR2G , Dual D−Type Positive Edge−Triggered Flip−Flop
MC74AC74DTR2 ,Dual D-Type Positive Edge Trigger3MC74AC74, MC74ACT74AC CHARACTERISTICS (For Figures and Waveforms – See Section 3 of the ON Semicon ..
MC74AC74MEL ,Dual D-Type Positive Edge Triggerpositive edge of the clock pulse. Clock triggering occurs at a voltagelevel of the clock pulse and ..
MC74AC74N ,DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP * DUAL D-TYPE POSITIVEEDGE-TRIGGEREDThe MC74AC74/74ACT74 is a dual D-type flip-flop with Asynch ..
MCP2140 , Infrared Encoder/Decoder
MCP2551 , High-Speed CAN Transceiver
MCP3010 , NON-ZERO-CROSSING TRIACS
MCP3010 , NON-ZERO-CROSSING TRIACS
MCP3010 , NON-ZERO-CROSSING TRIACS
MCP6002-I/MS , 1 MHz Bandwidth Low Power Op Amp
MC74AC74D-MC74AC74N-MC74ACT74D
DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
- - -The MC74AC74/74ACT74 is a dual D-type flip-flop with Asynchronous Clear
and Set inputs and complementary (Q,Q) outputs. Information at the input is
transferred to the outputs on the positive edge of the clock pulse. Clock triggering
occurs at a voltage level of the clock pulse and is not directly related to the transition
time of the positive-going pulse. After the Clock Pulse input threshold voltage has
been passed, the Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the Clock Pulse input.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH Outputs Source/Sink 24 mA ′ACT74 Has TTL Compatible Inputs
VCC
CD1 D1 CP1 SD1 Q1 Q1
CD2 D2 CP2 SD2 Q2 Q2
GND
PIN NAMESD1, D2 Data Inputs Clock Pulse Inputs Direct Clear Inputs
SD1, SD2 Direct Set Inputs
Q1, Q1, Q2, Q2 Outputs
TRUTH TABLE (Each Half)H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Q0(Q0) = Previous Q(Q) before
LOW-to-HIGH Transition of Clock
LOGIC SYMBOL
