MC74ACT273ML1 ,Octal D Flip FlopLOGIC DIAGRAMD D D D D D D D0 1 2 3 4 5 6 7CPD Q D Q D Q D Q D Q D Q D Q D QCP CP CP CP CP CP CP CP ..
MC74ACT273ML1 ,Octal D Flip Flop* ** * OCTAL D FLIP-FLOPThe MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops with indi ..
MC74ACT273N ,OCTAL D FLIP-FLOPLOGIC DIAGRAMD D D D D D D D0 1 2 3 4 5 6 7CPD Q D Q D Q D Q D Q D Q D Q D QCP CP CP CP CP CP CP CP ..
MC74ACT273N ,OCTAL D FLIP-FLOPMAXIMUM RATINGS*Symbol Parameter Value UnitV DC Supply Voltage (Referenced to GND) –0.5 to +7.0 VCC ..
MC74ACT299DWR2 ,8-Input Universal Shift/Storage Register with Common Parallel I/O Pinshold (store), shift left, shift right and load data. The parallel load inputsand flip−flop outputs ..
MC74ACT32 ,Quad 2-Input OR Gate with TTLMaximum Ratings are those values beyond which damage to the device mayoccur. Functional operation s ..
MCP6002-I/MS , 1 MHz Bandwidth Low Power Op Amp
MCP6002I/SN , 1 MHz Bandwidth Low Power Op Amp
MCP6002I/SN , 1 MHz Bandwidth Low Power Op Amp
MCP6002-I/SN , 1 MHz Bandwidth Low Power Op Amp
MCP6002-I/SN , 1 MHz Bandwidth Low Power Op Amp
MCP6002-I/SN , 1 MHz Bandwidth Low Power Op Amp
MC74ACT273ML1
Octal D Flip Flop
-The MC74AC273/74ACT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered Clock (CP) and Master
Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time
before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-
flop’s Q output.
All outputs will be forced LOW independently of Clock or Data inputs by a LOW
voltage level on the MR input. The device is useful for applications where the true
output only is required and the Clock and Master Reset are common to all storage
elements. Ideal Buffer for MOS Microprocessor or Memory Eight Edge-Triggered D Flip-Flops Buffered Common Clock Buffered, Asynchronous Master Reset See MC74AC377 for Clock Enable Version See MC74AC373 for Transparent Latch Version See MC74AC374 for 3-State Version Outputs Source/Sink 24 mA ′ACT273 Has TTL Compatible Inputs
VCC D7 D6 Q6 Q5 D5 D4 Q4 CP Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND
PIN NAMESD0–D7 Data Inputs Master Reset Clock Pulse Input
Q0–Q7 Data Outputs
LOGIC SYMBOL
