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MC74AC74DR2 from MOT, Motorola 8995pcs , SOP,Dual D-Type Positive Edge Trigger
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MC74AC74DR2 MOT N/a 8995
MC74AC74DR2 from ON, ON Semiconductor 2400pcs , SOP-14,Dual D-Type Positive Edge Trigger
MC74AC74DR2 from MOTORML, Motorola 594pcs , 3.9MM14,Dual D-Type Positive Edge Trigger
MC74AC74, MC74ACT74Dual D-Type PositiveEdge-Triggered Flip-FlopThe MC74AC74/74ACT74 is a dual D–type flip–flop withAsynchronous Clear and Set inputs and complementary (Q,Q)outputs. Information at the input is transferred to the outputs on the3MC74AC74, MC74ACT74AC CHARACTERISTICS (For Figures and Waveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)74AC 74ACT = –40°CAT = +25°CV * Fig.ACCSymbol Parameter to +85°C Unit(V) C = 50 pF No.LC = 50 pFLMin Typ Max Min MaxMaximum Clock 3.3 100 125 – 95 –ff MHz MHz 3 3– –3 3ma max xFrequency 5.0 140 160 – 125 –3.3 5.0 8.0 12.5 4.0 13.0Propagation Delay gytt ns ns 3 3– –6 6PL PLH HC or S to Q or Q 5.0 3.5 6.0 9.0 3.0 10.0Dn Dn n n3.3 4.0 10.5 12.0 3.5 13.5Propagation Delay gytt ns ns 3 3– –6 6PHL PHLC or S to Q or Q 5.0 3.0 8.0 9.5 2.5 10.5Dn Dn n n3.3 4.5 8.0 13.5 4.0 16.0Propagation Delay gytt ns ns 3 3– –6 6PL PLH HC to Q or Q 5.0 3.5 6.0 10.0 3.0 10.5Pn n n3.3 3.5 8.0 14.0 3.5 14.5Propagation Delay gytt ns ns 3 3– –6 6PHL PHLC to Q or Q 5.0 2.5 6.0 10.0 2.5 10.5Pn n n*Voltage Range 3.3 V is 3.3 V ±0.3 V.Voltage Range 5.0 V is 5.0 V ±0.5 V.AC OPERATING REQUIREMENTS74AC 74ACT = –40°CAV * T = +25°C Fig.CC Ato +85°CSymbol Parameter Unit(V) C = 50 pF No.LC = 50 pFLTyp Guaranteed MinimumSet-up Time, HIGH or LOW 3.3 1.5 4.0 4.5tt ns ns 3–9 3–9s sD to CP 5.0 1.0 3.0 3.0n nHold Time, HIGH or LOW 3.3 –2.0 0.5 0.5tt ns ns 3–9 3–9h hD to CP 5.0 –1.5 0.5 0.5n nC or C or S 3.3 3.0 5.5 7.0Pn Dn Dntt ns ns 3 3–6 –6w wPulse Width 5.0 2.5 4.5 5.0Recovery TIme 3.3 –2.5 0 0tt ns ns 3–9 3–9re rec cC or S to CP 5.0 –2.0 0 0Dn Dn*Voltage Range 3.3 V is 3.3 V ±0.3 V.Voltage Range 5.0 V is 5.0 V ±0.5 V.positive edge of the clock pulse. Clock triggering occurs at a voltagelevel of the clock pulse and is not directly related to the transitionPDIP–14time of the positive-going pulse. After the Clock Pulse inputN SUFFIXthreshold voltage has been passed, the Data input is locked out andCASE 646information present will not be transferred to the outputs until the 14next rising edge of the Clock Pulse input.1Asynchronous Inputs:SO–14LOW input to S (Set) sets Q to HIGH levelD SUFFIXD14CASE 751ALOW input to C (Clear) sets Q to LOW levelD1Clear and Set are independent of clockSimultaneous LOW on C and S makes both Q and Q HIGHD DTSSOP–1414• Outputs Source/Sink 24 mA DT SUFFIXCASE 948G1• ′ACT74 Has TTL Compatible InputsVC D CP S Q QCC EIAJ–14D2 2 2 D2 2 2M SUFFIX14 13 12 11 10 9 814CASE 9651C SD1 D2D Q CP Q1 1 2 2CP Q D Q ORDERING INFORMATION1 S 1 C2 2D1 D2Device Package ShippingMC74AC74N PDIP–14 25 Units/Rail1 2 34567C D CP S Q Q GNDMC74ACT74N PDIP–14 25 Units/RailD1 1 1 D1 1 1MC74AC74D SOIC–14 55 Units/RailFigure 1. Pinout: 14–Lead Packages Conductors(Top View) MC74AC74DR2 SOIC–14 2500 Tape & ReelMC74ACT74D SOIC–14 55 Units/RailPIN ASSIGNMENTMC74ACT74DR2 SOIC–14 2500 Tape & ReelPIN FUNCTIONMC74AC74DT TSSOP–14 96 Units/RailD , D Data Inputs1 2MC74AC74DTR2 TSSOP–14 2500 Tape & ReelCP , CP Clock Pulse Inputs1 2C , C Direct Clear Inputs MC74ACT74DT TSSOP–14 96 Units/RailD1 D2S , S Direct Set InputsMC74ACT74DTR2 TSSOP–14 2500 Tape & ReelD1 D2Q , Q , Q , Q Outputs1 1 2 2MC74AC74M EIAJ–14 50 Units/RailMC74AC74MEL EIAJ–14 2000 Tape & ReelMC74ACT74M EIAJ–14 50 Units/RailMC74ACT74MEL EIAJ–14 2000 Tape & ReelDEVICE MARKING INFORMATIONSee general marking information in the device markingsection on page 7 of this data sheet. Semiconductor Components Industries, LLC, 20011 Publication Order Number:May, 2001 – Rev. 5 MC74AC74/DMC74AC74, MC74ACT74TRUTH TABLE (Each Half)Inputs OutputsQ Q1 1S CD1 D1S C CP D Q QD DD CP1 1L H X X H LH L X X L HL L X X H HH H H H LH H L L HQ QH H L X Q Q0 0 2 2S CDD2 2NOTE: H = HIGH Voltage LevelD CP2 2L = LOW Voltage LevelX = Immaterial; = LOW-to-HIGH Clock TransitionQ (Q ) = Previous Q(Q) before LOW-to-HIGH 0 0Transition of ClockFigure 2. Logic SymbolSDD QCPQCDNOTE: This diagram is provided only for the understanding oflogic operations and should not be used to estimatepropagation delays.Figure 3.
MC74AC74DR2 ON,3MC74AC74, MC74ACT74AC CHARACTERISTICS (For Figures and Waveforms – See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)74AC 74ACT = –40°CA ..

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