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MC68HC812A4CPV8Freescale N/a213avai16-bit microcontroller
MC68HC812A4CPV8MOTN/a1800avai16-bit microcontroller


MC68HC812A4CPV8 ,16-bit microcontroller**Order this documentSEMICONDUCTOR TECHNICAL DATAby MCM63P631A/DMCM63P631AProduct Preview64K x 32 B ..
MC68HC908AB32 ,MC68HC908AB32 HCMOS Microcontroller UnitGeneral Description . . . . . . . . . . . . . . . . . . . .29Section 2. Memory Map . . . . . . . . ..
MC68HC908AB32CFU ,HCMOS Microcontroller UnitGeneral Description . . . . . . . . . . . . . . . . . . . .29Section 2. Memory Map . . . . . . . . ..
MC68HC908AB32MFU ,HCMOS Microcontroller UnitGeneral Description . . . . . . . . . . . . . . . . . . . .29Section 2. Memory Map . . . . . . . . ..
MC68HC908AP16CB ,Microcontrollers Freescale Semiconductor, Inc.MC68HC908AP64MC68HC908AP32MC68HC908AP16MC68HC908AP8Data SheetM68HC ..
MC68HC908AP16CFB ,MicrocontrollersElectrical Specifications — Added run and wait 421I data for 8MHz at 3V.DDSection 24.
MCH6610 ,Ultrahigh-Speed Switching ApplicationsAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
MCH6611 ,Ultrahigh-Speed Switching ApplicationsAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
MCH6613 ,Power MOSFET 30V, 0.35A, 3.7Ohm,-30V, -0.2A, 10.4Ohm, Complementary Dual MCPH6Absolute Maximum Ratings at Ta=25°CParameter Symbol Conditions N-channel P-channel UnitDrain-to-Sou ..
MCH6613-TL-E , Power MOSFET
MCH6614 ,Ultrahigh-Speed Switching ApplicationsAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions N-channel P-channel UnitDrain-to-Sou ..
MCH6615 ,Ultrahigh-Speed Switching ApplicationsAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions N-channel P-channel UnitDrain-to-Sou ..


MC68HC812A4CPV8
16-bit microcontroller
**Order this documentSEMICONDUCTOR TECHNICAL DATAby MCM63P631A/DMCM63P631AProduct Preview64K x 32 Bit Pipelined BurstRAMSynchronous Fast Static RAMThe MCM63P631A is a 2M bit synchronous fast static RAM designed to pro-vide a burstable, high performance, secondary cache for the 68K Family, Pow-TQ PACKAGEerPC, and Pentium microprocessors. It is organized as 64K words of 32 bitsTQFPeach. This device integrates input registers, an output register, a 2–bit addressCASE 983A–01counter, and high speed SRAM onto a single monolithic circuit for reduced partscount in cache data RAM applications. Synchronous design allows precise cyclecontrol with the use of an external clock (K). CMOS circuitry reduces the overallpower consumption of the integrated functions for greater reliability.Addresses (SA), data inputs (DQx), and all control signals except outputenable (G), sleep mode (ZZ), and Linear Burst Order (LBO) are clock (K) con-trolled through positive–edge–triggered noninverting registers.Bursts can be initiated with either ADSP or ADSC input pins. Subsequent burstaddresses can be generated internally by the MCM63P631A (burst sequenceoperates in linear or interleaved mode dependent upon state of LBO) and con-trolled by the burst address advance (ADV) input pin.Write cycles are internally self–timed and are initiated by the rising edge of theclock (K) input. This feature eliminates complex off–chip write pulse generationand provides increased timing flexibility for incoming signals.Synchronous byte write (SBx), synchronous global write (SGW), and synchro-nous write enable SW are provided to allow writes to either individual bytes or toall bytes. The four bytes are designated as “a”, “b”, “c”, and “d”. SBa controlsDQa, SBb controls DQb, etc. Individual bytes are written if the selected bytewrites SBx are asserted with SW. All bytes are written if either SGW is assertedor if all SBx and SW are asserted.For read cycles, pipelined SRAMs output data is temporarily stored by anedge–triggered output register and then released to the output buffers at the nextrising edge of clock (K).The MCM63P631A operates from a 3.3 V power supply, all inputs and outputsare LVTTL compatible.• MCM63P631A–117 = 4.5 ns access / 8.5 ns cycle (117 MHz)MCM63P631A–100 = 4.5 ns access / 10 ns cycle (100 MHz)MCM63P631A–75 = 7 ns access / 13.3 ns cycle (75 MHz)MCM63P631A–66 = 8 ns access / 15 ns cycle (66 MHz)• Single 3.3 V + 10%, – 5% Power Supply• ADSP, ADSC, and ADV Burst Control Pins• Selectable Burst Sequencing Order (Linear/Interleaved)• Internally Self–Timed Write Cycle• Byte Write and Global Write Control• Sleep Mode (ZZ)• PB1 Version 2.0 Compatible• Single–Cycle Deselect Timing• JEDEC Standard 100–Pin TQFP PackageThe PowerPC name is a trademark of IBM Corp., used under license therefrom.Pentium is a trademark of Intel Corp.This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.9/30/97 Motorola, Inc. 1997MOTOROLA FAST SRAM MCM63P631A1FUNCTIONAL
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