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MC68HC68MOTN/a80avaiReal-Time Clock plus RAM with Serial Interface
MC68HC68T1MOTON/a6avaiReal-Time Clock plus RAM with Serial Interface


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MC68HC68-MC68HC68T1
Real-Time Clock plus RAM with Serial Interface
**Order this documentby MC68HC68T1/DSEMICONDUCTOR TECHNICAL DATA* ** * P SUFFIXPLASTIC DIPCMOS16 CASE 6481The MC68HC68T1 HCMOS Clock/RAM peripheral contains a real–timeclock/calendar, a 32 x 8 static RAM, and a synchronous, serial, three–wireinterface for communication with a microcontroller or processor. Operating in aDW SUFFIX16burst mode, successive Clock/RAM locations can be read or written using onlySOG PACKAGEa single starting address. An on–chip oscillator allows acceptance of a CASE 751G1selectable crystal frequency or the device can be programmed to accept a50/60 Hz line input frequency.ORDERING INFORMATIONThe LINE and system voltage (V ) pins give the MC68HC68T1 theSYSMC68HC68T1P Plastic DIPcapability for sensing power–up/power–down conditions, a capability useful forMC68HC68T1DW SOG Packagebattery–backup systems. The device has an interrupt output capable ofsignaling a microcontroller or processor of an alarm, periodic interrupt, or powersense condition. An alarm can be set for comparison with the seconds, minutes,and hours registers. This alarm can be used in conjunction with the powerPIN ASSIGNMENTsupply enable (PSE) output to initiate a system power–up sequence if the VSYSCLKOUT 1 16 VDDpin is powered to the proper level.A software power–down sequence can be initiated by setting a bit in the CPUR 2 15XTALoutinterrupt control register. This applies a reset to the CPU via the CPUR pin, setsINT 3 14 XTALinthe clock out (CLKOUT) and PSE pins low, and disables the serial interface.SCK 4 13 VBATTThis condition is held until a rising edge is sensed on the V input pin,SYSsignaling system power coming on, or by activation of a previously enabledMOSI 5 12VSYSinterrupt if the V pin is powered up.SYSMISO 6 11 LINEA watchdog circuit can be enabled that requires the microcontroller orSS 7 10PORprocessor to toggle the slave select (SS) pin of the MC68HC68T1 periodicallywithout performing a serial transfer. If this condition is not met, the CPUR lineV 8 9 PSESSresets the CPU.• Full Clock
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