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Partno	Mfg	Dc	Qty	Available	Descript
MC54HC367	MOT?	N/a	30	avai	Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit Sections
MC54HC367J	MOT	N/a	20	avai	Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit Sections
MC74HC367		N/a	900	avai	Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit Sections
MC74HC367	MOT	N/a	29	avai	Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit Sections
MC74HC367N	MOT	N/a	273	avai	Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit Sections

MC74HC367 ,Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit SectionsLOGIC DIAGRAMY0 3 14 A5A1 4 13 Y52 3A0 Y0Y1 5 12 A4A2 6 11 Y44 5A1 Y1Y2 7 10 A36 7GND 8 9 Y3A2 Y210 ..
MC74HC367 ,Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit Sections**SEMICONDUCTOR TECHNICAL DATA**& "*"* **$* "*# %*"* * *"* *"J SUFFIX *" "!CERAMIC PACKAGEHigh–Per ..
MC74HC367N ,Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit SectionsMAXIMUM RATINGS*ÎÎÎSymbol Parameter Value UnitThis device contains protectionÎÎÎÎÎÎcircuitry to gua ..
MC74HC368 ,Hex 3-State Inverting Buffer with Separate 2-Bit and 4-Bit SectionsELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaran ..
MC74HC368N ,Hex 3-State Inverting Buffer with Separate 2-Bit and 4-Bit SectionsELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ..
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MC54HC367-MC54HC367J-MC74HC367-MC74HC367N
Hex 3-State Noninverting Buffer with Separate 2-Bit and 4-Bit Sections
SEMICONDUCTOR TECHNICAL DATA"" $ "
# %" " "" "!
High–Performance Silicon–Gate CMOS
The MC54/74HC367 is identical in pinout to the LS367. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device is arranged into 2–bit and 4–bit sections, each having its own
active–low Output Enable. When either of the enables is high, the affected
buffer outputs are placed into high–impedance states. The HC367 has
noninverting outputs. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 μA High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard
No. 7A Chip Complexity: 92 FETs or 23 Equivalent Gates
LOGIC DIAGRAM
OUTPUT ENABLE 1
OUTPUT ENABLE 2
PIN 8 = GND

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