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MC1670LMOTON/a5avaiMaster-Slave Flip-Flop


MC1670L ,Master-Slave Flip-FlopLOGIC DIAGRAMH L X X LH H X X N.D.L L L L Q 5 SnL L L LHL L L Qn7 C1L L H L QnQ 29 C2L L H HL L H H ..
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MC1670L
Master-Slave Flip-Flop
SEMICONDUCTOR TECHNICAL DATA-
Master slave construction renders the MC1670 relatively insensitive to the
shape of the clock waveform, since only the voltage levels at the clock inputs
control the transfer of information from data input (D) to output.
When both clock inputs (C1 and C2) are in the low state, the data input
affects only the “Master” portion of the flip-flop. The data present in the “Master”
is transferred to the “Slave” when clock inputs (C1 “OR” C2) are taken from a
low to a high level. In other words, the output state of the flip-flop changes on the
positive transition of the clock pulse.
While either C1 “OR” C2 is in the high state, the “Master” (and data input) is
disabled.
Asynchronous Set (S) and Reset (R) override Clock (C) and Data (D) inputs.
Power Dissipation = 220 mW typ (No Load)
fTog = 350 MHz typ
TRUTH TABLE

ND = Not Defined
C = C1 + C2
ELECTRICAL CHARACTERISTICS
LOGIC DIAGRAM

VCC2 = Pin 16
VEE = Pin 8
PIN ASSIGNMENT
VCC1
RESET
SET
VEE
VCC2
DATA
CLOCK 2
CLOCK 1
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