MC14572UBD ,Hex Gate**SEMICONDUCTOR TECHNICAL DATA *L SUFFIXThe MC14572UB hex functional gate is constructed with MOS P ..
MC14572UBD ,Hex GateMaximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating: ..
MC14572UBDR2G , Hex Gate
MC14573 ,CMOS MSI(PROGRAMMABLE DUAL OP AMP / DUAL COMPARATORMOTOROLAI SEMICONDUCTOR -i--i-l-ll-ll-lellMl.TECHNICAL DATAMCI4573MCI4574MC14575.1QUAD PROGRAMMABLE ..
MC14573D ,CMOS MSI(PROGRAMMABLE DUAL OP AMP / DUAL COMPARATORMOTOROLAI SEMICONDUCTOR -i--i-l-ll-ll-lellMl.TECHNICAL DATAMCI4573MCI4574MC14575.1QUAD PROGRAMMABLE ..
MC14573P ,CMOS MSI(PROGRAMMABLE DUAL OP AMP / DUAL COMPARATORMAXIMUM RATINGS? (Voltages referenced to V531Rating 7 Symbol Value UnitDC Supply Voltage VDD 7 0 51 ..
MC74AC573DWR2 ,Octal Buffer/Line Driver with 3-State OutputsFUNCTIONAL DESCRIPTIONTRUTH TABLEThe MC74AC573/74ACT574 contains eight D–typeInputs Outputslatches ..
MC74AC573DWR2 ,Octal Buffer/Line Driver with 3-State OutputsMAXIMUM RATINGS*Symbol Parameter Value UnitV DC Supply Voltage (Referenced to GND) –0.5 to +7.0 VCC ..
MC74AC573DWR2 ,Octal Buffer/Line Driver with 3-State OutputsMaximum Ratings are those values beyond which damage to the device may occur. Functional operation ..
MC74AC573MEL , OCTAL D-TYPE LATCH WITH 3-STATE OUTPUTS
MC74AC573N ,Octal Buffer/Line Driver with 3-State Outputshttp://onsemi.com2MC74AC573, MC74ACT573RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ M ..
MC74AC574 ,Octal D-Type Flip Flop with 3-State Outputsstored in the flip–flops on the LOW–to–HIGH Clock (CP) transition.PDIP–20The MC74AC574/74ACT574 is ..
MC14572UBCL-MC14572UBCP-MC14572UBD
Hex Gate
-The MC14572UB hex functional gate is constructed with MOS P–channel
and N–channel enhancement mode devices in a single monolithic structure.
These complementary MOS logic gates find primary use where low power
dissipation and/or high noise immunity is desired. The chip contains four
inverters, one NOR gate and one NAND gate. Diode Protection on All Inputs Single Supply Operation Supply Voltage Range = 3.0 Vdc to 18 Vdc NOR Input Pin Adjacent to VSS Pin to Simplify Use As An Inverter NAND Input Pin Adjacent to VDD Pin to Simplify Use As An Inverter NOR Output Pin Adjacent to Inverter Input Pin For OR Application NAND Output Pin Adjacent to Inverter Input Pin For AND Application Capable of Driving Two Low–power TTL Loads or One Low–Power
Schottky TTL Load over the Rated Temperature Range
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125C
CIRCUIT SCHEMATICVDDVDD 14
VSSVSS
VSS
SEMICONDUCTOR TECHNICAL DATA
