MC14517BDW ,Dual 64-Bit Static Shift Register**SEMICONDUCTOR TECHNICAL DATA** * * ** * ** * * **The MC14517B dual 64–bit static shift register c ..
MC14518B ,Dual BCD Up CounterMaximum Ratings are those values beyond which damage to the device may occur.CLOCK11†Temperature De ..
MC14518B ,Dual BCD Up CounterMAXIMUM RATINGS* (Voltages Referenced to V )SSSymbol Parameter Value UnitV DC Supply Voltage – 0.5 ..
MC14518BCL ,Dual up counterMaximum Ratings are those values beyond which damage to the device may occur.CLOCK11†Temperature De ..
MC14518BCL ,Dual up counterMaximum Ratings are those values beyond which damage to the device may occur.CLOCK11†Temperature De ..
MC14518BCL ,Dual up counter**SEMICONDUCTOR TECHNICAL DATA** ** **The MC14518B dual BCD counter and the MC14520B dual binary co ..
MC68HC908JK3CP ,MC68HC908JK1General Description . . . . . . . . . . . . . . . . . . . .21Section 2. Memory . . . . . . . . . . ..
MC68HC908JK3ECP ,Microcontrollers
MC68HC908JK3ECP ,Microcontrollers
MC68HC908J-K3ECP ,Microcontrollers
MC68HC908JK3EMDW ,Microcontrollers
MC68HC908JK3MDW ,MC68HC908JK1 MC68HC908JL3/HRev. 1.0MC68HC908JK1MC68HRC908JK1MC68HC908JK3MC68HRC908JK3MC68HC908JL3MC68HRC908J ..
MC14517BCL-MC14517BDW
Dual 64-Bit Static Shift Register
-The MC14517B dual 64–bit static shift register consists of two identical,
independent, 64–bit registers. Each register has separate clock and write
enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data
input is entered by clocking, regardless of the state of the write enable input.
An output is disabled (open circuited) when the write enable input is high.
During this time, data appearing at the data input as well as the 16–bit,
32–bit, and 48–bit taps may be entered into the device by application of a
clock pulse. This feature permits the register to be loaded with 64 bits in 16
clock periods, and also permits bus logic to be used. This device is useful in
time delay circuits, temporary memory storage circuits, and other serial shift
register applications. Diode Protection on All Inputs Fully Static Operation Output Transitions Occur on the Rising Edge of the Clock Pulse Exceedingly Slow Input Transition Rates May Be Applied to the Clock
Input 3–State Output at 64th–Bit Allows Use in Bus Logic Applications Shift Registers of any Length may be Fully Loaded with 16 Clock Pulses Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
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†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125C
FUNCTIONAL TRUTH TABLE (X = Don’t Care)
SEMICONDUCTOR TECHNICAL DATA
