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MC14517BMOTN/a46avaiDual 64-Bit Static Shift Register
MC14517BCPONN/a30074avaiDual 64-Bit Static Shift Register


MC14517BCP ,Dual 64-Bit Static Shift RegisterMaximum Ratings are those values beyond which damage to the devicemay occur.2. Temperature Derating ..
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MC14517B-MC14517BCP
Dual 64-Bit Static Shift Register
MC14517B
Dual 64-Bit Static Shift
Register
The MC14517B dual 64–bit static shift register consists of two
identical, independent, 64–bit registers. Each register has separate clock
and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data
at the data input is entered by clocking, regardless of the state of the write
enable input. An output is disabled (open circuited) when the write enable
input is high. During this time, data appearing at the data input as well as
the 16–bit, 32–bit, and 48–bit taps may be entered into the device by
application of a clock pulse. This feature permits the register to be loaded
with 64 bits in 16 clock periods, and also permits bus logic to be used.
This device is useful in time delay circuits, temporary memory storage
circuits, and other serial shift register applications. Diode Protection on All Inputs Fully Static Operation Output Transitions Occur on the Rising Edge of the Clock Pulse Exceedingly Slow Input Transition Rates May Be Applied to the
Clock Input 3–State Output at 64th–Bit Allows Use in Bus Logic Applications Shift Registers of any Length may be Fully Loaded with 16 Clock
Pulses Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Maximum Ratings are those values beyond which damage to the device
may occur. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/�C From 65�C To 125�C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS � (Vin or Vout) � VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
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