MC14516BCL ,Binary Up/Down CounterELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎΖ 55* C 25* C 125* CV VD DD DVdc VdcC ..
MC14516BCL ,Binary Up/Down CounterMaximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating: ..
MC14516BCL ,Binary Up/Down CounterBLOCK DIAGRAM• Single Pin Reset• Asynchronous Preset Enable Operation PE1 Q0 6• Capable of Driving ..
MC14516BCP ,Binary Up/Down CounterMAXIMUM RATINGS* (Voltages Referenced to V )SS10 UP/DOWNSymbol Parameter Value UnitCLOCK Q215 14V D ..
MC14516BFEL ,Binary Up/Down Counter
MC14516BFR1 ,Binary Up/Down CounterELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎ – 55* C 25* C 125* CV VDD DD(4.)VdcCh ..
MC68HC908JB8FB ,MICROCONTROLLERS
MC68HC908JB8FB ,MICROCONTROLLERS
MC68HC908JB8FB ,MICROCONTROLLERS
MC68HC908JB-8FB ,MICROCONTROLLERS
MC68HC908JK1CDW ,MC68HC908JK1General Description . . . . . . . . . . . . . . . . . . . .21Section 2. Memory . . . . . . . . . . ..
MC68HC908JK1CP ,MC68HC908JK1General Description . . . . . . . . . . . . . . . . . . . .21Section 2. Memory . . . . . . . . . . ..
MC14516BCL-MC14516BCP
Binary Up/Down Counter
-The MC14516B synchronous up/down binary counter is constructed with
MOS P–channel and N–channel enhancement mode devices in a monolithic
structure.
This counter can be preset by applying the desired value, in binary, to the
Preset inputs (P0, P1, P2, P3) and then bringing the Preset Enable (PE)
high. The direction of counting is controlled by applying a high (for up
counting) or a low (for down counting) to the UP/DOWN input. The state of
the counter changes on the positive transition of the clock input.
Cascading can be accomplished by connecting the Carry Out to the
Carry In of the next stage while clocking each counter in parallel. The
outputs (Q0, Q1, Q2, Q3) can be reset to a low state by applying a high to the
reset (R) pin.
This CMOS counter finds primary use in up/down and difference counting.
Other applications include: (1) Frequency synthesizer applications where
low power dissipation and/or high noise immunity is desired, (2) Analog–to–
digital and digital–to–analog conversions, and (3) Magnitude and sign
generation. Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Internally Synchronous for High Speed Logic Edge–Clocked Design — Count Occurs on Positive Going Edge
of Clock Single Pin Reset Asynchronous Preset Enable Operation Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky Load Over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125C
TRUTH TABLEX = Don’t Care
NOTE: When counting up, the Carry Out signal is normally high and is low only
when Q0 through Q3 are high and Carry In is low. When counting down,
SEMICONDUCTOR TECHNICAL DATA
