MC14511BDWR2 ,BCD/7 Segment LAT/Decoder/DriverMaximum Ratings).SSUnused inputs must always be tied to an appropriate logic voltage level (e.g., e ..
MC14511BDWR2 ,BCD/7 Segment LAT/Decoder/DriverThe circuit provides the functions of a 4–bit storage latch, an 8421BCD–to–seven segment decoder, a ..
MC14511BDWR2G , BCD−To−Seven Segment Latch/Decoder/Driver
MC14511BFR1 ,BCD-to-Seven Segment Latch/Decoder/DriverELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎ – 55* C 25* C 125* CV VDD DD(5.)VdcCh ..
MC14512 ,8-Channel Data SelectorELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎΖ 55* C 25* C 125* CV VD DD DVdc VdcC ..
MC14512B ,8-Channel Data SelectorELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎ – 55C 25C 125CV VDD DD(4.)Vdc Min ..
MC68HC711E9MFN2 ,Microcontroller, 2 MHz, RAM=512, ROM=0, EPROM=12K, EEPROM=512M68HC11E FamilyTechnical DataM68HC11MicrocontrollersM68HC11E/DRev. 4, 7/2002WWW.MOTOROLA.COM/SEMICO ..
MC68HC711E9MFN2 ,Microcontroller, 2 MHz, RAM=512, ROM=0, EPROM=12K, EEPROM=512M68HC11E FamilyTechnical DataM68HC11MicrocontrollersM68HC11E/DRev. 4, 7/2002WWW.MOTOROLA.COM/SEMICO ..
MC68HC711E9VFN2 ,Microcontroller, 2 MHz, RAM=512, ROM=0, EPROM=12K, EEPROM=512M68HC11E FamilyTechnical DataM68HC11MicrocontrollersM68HC11E/DRev. 4, 7/2002WWW.MOTOROLA.COM/SEMICO ..
MC68HC711E9VFN2 ,Microcontroller, 2 MHz, RAM=512, ROM=0, EPROM=12K, EEPROM=512M68HC11E FamilyTechnical DataM68HC11MicrocontrollersM68HC11E/DRev. 4, 7/2002WWW.MOTOROLA.COM/SEMICO ..
MC68HC711E9VFN2 ,Microcontroller, 2 MHz, RAM=512, ROM=0, EPROM=12K, EEPROM=512M68HC11E FamilyTechnical DataM68HC11MicrocontrollersM68HC11E/DRev. 4, 7/2002WWW.MOTOROLA.COM/SEMICO ..
MC68HC711E9VFN2 ,Microcontroller, 2 MHz, RAM=512, ROM=0, EPROM=12K, EEPROM=512M68HC11E FamilyTechnical DataM68HC11MicrocontrollersM68HC11E/DRev. 4, 7/2002WWW.MOTOROLA.COM/SEMICO ..
MC14511B-MC14511BD-MC14511BDWR2
BCD/7 Segment LAT/Decoder/Driver
MC14511B
BCD-T o-Seven Segment
Latch/Decoder/Driver
The MC14511B BCD–to–seven segment latch/decoder/driver is
constructed with complementary MOS (CMOS) enhancement mode
devices and NPN bipolar output drivers in a single monolithic structure.
The circuit provides the functions of a 4–bit storage latch, an 8421
BCD–to–seven segment decoder, and an output drive capability. Lamp
test (LT), blanking (BI), and latch enable (LE) inputs are used to test the
display, to turn–off or pulse modulate the brightness of the display, and
to store a BCD code, respectively. It can be used with seven–segment
light–emitting diodes (LED), incandescent, fluorescent, gas discharge,
or liquid crystal readouts either directly or indirectly.
Applications include instrument (e.g., counter, DVM, etc.) display
driver, computer/calculator display driver, cockpit display driver, and
various clock, watch, and timer uses. Low Logic Circuit Power Dissipation High–Current Sourcing Outputs (Up to 25 mA) Latch Storage of Code Blanking Input Lamp Test Provision Readout Blanking on all Illegal Input Combinations Lamp Intensity Modulation Capability Time Share (Multiplexing) Facility Supply Voltage Range = 3.0 V to 18 V Capable of Driving Two Low–power TTL Loads, One Low–power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range Chip Complexity: 216 FETs or 54 Equivalent Gates Triple Diode Protection on all Inputs
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2) Maximum Ratings are those values beyond which damage to the device
may occur. Temperature Derating:
