MC14076BCP ,4-Bit D-Type Register with Three-State OutputsMaximum Ratings are those values beyond which damage to the device may occur.ÎÎÎ2 B OUTPUT†Temperat ..
MC14077B ,Quad Exclusive NOR GateFeatures14• Supply Voltage Range = 3.0 Vdc to 18 VdcPDIP−14• All Outputs Buffered MC140xxBCPP SUFFI ..
MC14077BAL ,CMOS SSI Quad Exclusive "OR" and "NOR" GatesMAXIMUM RATINGS* (Voltages Referenced to V ) SOICSSCASE 751AÎÎSymbol Parameter Value UnitÎÎÎÎÎV DC ..
MC14077BCL ,CMOS SSI Quad Exclusive "OR" and "NOR" GatesMaximum Ratings are those values beyond which damage to the device may occur.ÎÎÎGate Gate†Temperatu ..
MC14077BCL ,CMOS SSI Quad Exclusive "OR" and "NOR" GatesMAXIMUM RATINGS* (Voltages Referenced to V ) SOICSSCASE 751AÎÎSymbol Parameter Value UnitÎÎÎÎÎV DC ..
MC14077BCP ,CMOS SSI Quad Exclusive "OR" and "NOR" GatesMAXIMUM RATINGS* (Voltages Referenced to V ) SOICSSCASE 751AÎÎSymbol Parameter Value UnitÎÎÎÎÎV DC ..
MC68EC020FG25 ,MICROPROCESSORS USERS MANUALMC68020MC68EC020MICROPROCESSORSUSER’S MANUALFirst EditionMotorola reserves the right to make change ..
MC68EC020RP16 ,MICROPROCESSORS USERS MANUALMC68020MC68EC020MICROPROCESSORSUSER’S MANUALFirst EditionMotorola reserves the right to make change ..
MC68EC020RP25 ,MICROPROCESSORS USERS MANUALMC68020MC68EC020MICROPROCESSORSUSER’S MANUALFirst EditionMotorola reserves the right to make change ..
MC68EC020RP-25 ,MICROPROCESSORS USERS MANUALMC68020MC68EC020MICROPROCESSORSUSER’S MANUALFirst EditionMotorola reserves the right to make change ..
MC68EC030FE40C , Second-Generation 32-Bit Enhanced Embedded Controller
MC68EC030FE40C , Second-Generation 32-Bit Enhanced Embedded Controller
MC14076BCL-MC14076BCP
4-Bit D-Type Register with Three-State Outputs
! - -The MC14076B 4–Bit Register consists of four D–type flip–flops operating
synchronously from a common clock. OR gated output–disable inputs force
the outputs into a high–impedance state for use in bus organized systems.
OR gated data–disable inputs cause the Q outputs to be fed back to the D
inputs of the flip–flops. Thus they are inhibited from changing state while the
clocking process remains undisturbed. An asynchronous master root is
provided to clear all four flip–flops simultaneously independent of the clock
or disable inputs. Three–State Outputs with Gated Control Lines Fully Independent Clock Allows Unrestricted Operation for the Two
Modes: Parallel Load and Do Nothing Asynchronous Master Reset Four Bus Buffer Registers Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range
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ÎÎÎ Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125C
FUNCTION TABLEWhen either output disable A or B (or both) is (are) high the
output is disabled to the high–impedance state; however
sequential operation of the flip–flops is not affected.
X = Don’t Care.
SEMICONDUCTOR TECHNICAL DATA
