MC14069UBFR2 ,Hex InverterELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎÎ – 55* CÎÎ 25* CÎÎÎÎÎ 125* CÎÎÎSymbo ..
MC14070 ,CMOS SSI Quad Exclusive "OR" and "NOR" Gates**SEMICONDUCTOR TECHNICAL DATA **Quad Exclusive “OR” and “NOR” GatesThe MC14070B quad exclusive OR ..
MC14070B ,Quad XOR GateMaximum ratings applied to the device are individual stress limit values (not dimensions section on ..
MC14070BAL ,Quad exclusive OR gateMaximum Ratings are those values beyond which damage to 1ha devlca may occur.tTemperature Davallng: ..
MC14070BCL ,CMOS SSI Quad Exclusive "OR" and "NOR" GatesMaximum Ratings are those values beyond which damage to the device may occur.ÎÎÎGate Gate†Temperatu ..
MC14070BCP ,CMOS SSI Quad Exclusive "OR" and "NOR" GatesMAXIMUM RATINGS* (Voltages Referenced to V ) SOICSSCASE 751AÎÎSymbol Parameter Value UnitÎÎÎÎÎV DC ..
MC68CK16Z4CPV16 , Symbols and Operators, CPU16 Register Mnemonics
MC68CK16Z4CPV16 , Symbols and Operators, CPU16 Register Mnemonics
MC68EC000FU10 ,Microprocessor, 16-/ 32-bit data and address registers, 16-Mbyte direct addressing range, memory-mapped input/output (I/O), 14 addressing modes, 10MHz
MC68EC000FU10 ,Microprocessor, 16-/ 32-bit data and address registers, 16-Mbyte direct addressing range, memory-mapped input/output (I/O), 14 addressing modes, 10MHz
MC68EC000FU8 ,Microprocessor, 16-/ 32-bit data and address registers, 16-Mbyte direct addressing range, memory-mapped input/output (I/O), 14 addressing modes, 8MHz
MC68EC000FU8 ,Microprocessor, 16-/ 32-bit data and address registers, 16-Mbyte direct addressing range, memory-mapped input/output (I/O), 14 addressing modes, 8MHz
MC14069UBFR2
Hex Inverter
-The MC14069UB hex inverter is constructed with MOS P–channel
and N–channel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays. Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low–Power TTL Loads or One Low–Power
Schottky TTL Load Over the Rated Temperature Range Triple Diode Protection on All Inputs Pin–for–Pin Replacement for CD4069UB Meets JEDEC UB Specifications
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Maximum Ratings are those values beyond which damage to the device
may occur. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
