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MC14050BFL1-MC14050BFR1-MC14050BFR2 Fast Delivery,Good Price
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MC14050BFL1MOTN/a852avaiHex Buffer
MC14050BFR1MOTN/a30avaiHex Buffer
MC14050BFR2MOTN/a2000avaiHex Buffer


MC14050BFR2 ,Hex Buffer3MC14049B, MC14050B(7.)ÎÎÎÎÎ AC SWITCHING CHARACTERISTICS (C = 50 pF, T = + 25* C)L AÎ VÎDD(8.)Cha ..
MC14051 ,Analog Multiplexers/DemultiplexersMaximum Ratings are those values beyond which damage to the devicedimensions section on page 12 of ..
MC14051 ,Analog Multiplexers/DemultiplexersMaximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating: ..
MC14051B ,Analog MultiplexerDemultiplexerMC14051B, MC14052B,MC14053BAnalogMultiplexers/DemultiplexersThe MC14051B, MC14052B, and MC14053B an ..
MC14051BCL ,Analog Multiplexers / DemultiplexersMaximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating: ..
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MC14050BFL1-MC14050BFR1-MC14050BFR2
Hex Buffer
--The MC14049B Hex Inverter/Buffer and MC14050B Noninverting
Hex Buffer are constructed with MOS P–Channel and N–Channel
enhancement mode devices in a single monolithic structure. These
complementary MOS devices find primary use where low power
dissipation and/or high noise immunity is desired. These devices
provide logic level conversion using only one supply voltage, VDD.
The input–signal high level (VIH) can exceed the VDD supply
voltage for logic level conversions. Two TTL/DTL loads can be driven
when the devices are used as a CMOS–to–TTL/DTL converter (VDD
= 5.0 V , VOL 0.4 V, IOL ≥ 3.2 mA).
Note that pins 13 and 16 are not connected internally on these
devices; consequently connections to these terminals will not affect
circuit operation. High Source and Sink Currents High–to–Low Level Converter Supply Voltage Range = 3.0 V to 18 V VIN can exceed VDD Meets JEDEC B Specifications Improved ESD Protection On All Inputs
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Maximum Ratings are those values beyond which damage to the device
may occur. Temperature Derating: See Figure 3.
This device contains protection circuitry to protect the inputs against damage
due to high static voltages or electric fields referenced to the VSS pin only. Extra
precautions must be taken to avoid applications of any voltage higher than the
maximum rated voltages to this high–impedance circuit. For proper operation, the
ranges VSS ≤ Vin ≤ 18 V and VSS ≤ Vout ≤ VDD are recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
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