MC14049UBFL1 ,Hex BuffersELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎÎ – 55* CÎÎ 25* CÎÎÎÎÎ 125* CÎÎÎV VDD ..
MC14049UBFL1 ,Hex Buffers2MC14049UB(7.)ÎÎÎÎÎ SWITCHING CHARACTERISTICS (C = 50 pF, T = 25* C)L AÎ VÎDD(8.)Characteristic Sy ..
MC1404P5 ,PRECISION LOW DRIFT VOLTAGE REFERENCES
MC14050B ,Hex Non-Inverter BufferELECTRICAL CHARACTERISTICS (Voltages Referenced to V )SSÎÎÎÎÎÎ – 55CÎÎ + 25CÎÎÎÎÎ + 125CÎÎÎV VDD ..
MC14050BCL ,Hex bufferLOGIC DIAGRAMMC14049B MC14050B3 2 3 25 4 5 47 6 7 69 10 9 1011 12 11 1214 15 14 15NC = PIN 13, 16 N ..
MC14050BCP ,Hex Non-Inverter BufferMaximum Ratings are those values beyond which damage to the device may occur.2Temperature Derating: ..
MC68701CL-1 ,MICROCOMPUTER WITH EPROM
MC68701CS ,V(cc / in): -0.3 to +7V; microcontroller unit (MCU)
MC68701S-1 ,V(cc / in): -0.3 to +7V; microcontroller unit (MCU)
MC68701S-1 ,V(cc / in): -0.3 to +7V; microcontroller unit (MCU)
MC68705P3 ,8-Bit EPROM Microcomputer Unit
MC68705P3CS ,8-Bit EPROM Microcomputer Unit
MC14049UBFL1
Hex Buffers
-The MC14049UB hex inverter/buffer is constructed with MOS
P–channel and N–channel enhancement mode devices in a single
monolithic structure. This complementary MOS device finds primary
use where low power dissipation and/or high noise immunity is
desired. This device provides logic–level conversion using only one
supply voltage, VDD. The input–signal high level (VIH) can exceed the
VDD supply voltage for logic–level conversions. Two TTL/DTL
Loads can be driven when the device is used as CMOS–to–TTL/DTL
converters (VDD = 5.0 V , VOL 0.4 V , IOL ≥ 3.2 mA). Note that pins
13 and 16 are not connected internally on this device; consequently
connections to these terminals will not affect circuit operation. High Source and Sink Currents High–to–Low Level Converter Supply Voltage Range = 3.0 V to 18 V Meets JEDEC UB Specifications VIN can exceed VDD Improved ESD Protection on All Inputs
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Maximum Ratings are those values beyond which damage to the device
may occur. Temperature Derating:
All Packages: See Figure 4.
This device contains circuitry to protect the inputs against damage due to high
static voltages or electric fields referenced to the VSS pin, only. Extra precautions
must be taken to avoid applications of any voltage higher than the maximum rated
voltages to this high–impedance circuit. For proper operation, the ranges VSS
Vin 18 V and VSS Vout VDD are recommended.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
