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MC10H161MMOTON/a350avaiBinary to 1-8 Decoder (Low)


MC10H161M ,Binary to 1-8 Decoder (Low)3MC10H161PACKAGE DIMENSIONSPLCC–20FN SUFFIXPLASTIC PLCC PACKAGECASE 775–02ISSUE CM S S0.007 (0.180) ..
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MC3487N ,Quadruple Differential Line Drivermaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..


MC10H161M
Binary to 1-8 Decoder (Low)
---The MC10H161 provides parallel decoding of a three bit binary
word to one of eight lines. The MC10H161 is useful in high–speed
multiplexer/demultiplexer applications.
The MC10H161 is designed to decode a three bit input word to one
of eight output lines. The MC10H161 output will be low when
selected while all other output are high. The enable inputs, when either
or both are high, force all outputs high.
The MC10H161 is a true parallel decoder. This eliminates unequal
parallel path delay times found in other decoder designs. These
devices are ideally suited for multiplexer/demultiplexer applications. Propagation Delay, 1.0 ns Typical Power Dissipation, 315 mW Typical (same as MECL 10K) Improved Noise Margin 150 mV (Over Operating Voltage and
Temperature Range) Voltage Compensated MECL 10K–Compatible
LOGIC DIAGRAM
DIP PIN ASSIGNMENT

VCC1
VEE
VCC2
VCC1=Pin 1
VCC2= Pin 16
VEE=Pin 8
E02
E115
C14
6Q0
5Q1
4Q2
3Q3Q4Q5Q6Q7
TRUTH TABLE

Pin assignment is for Dual–in–Line
Package. For PLCC pin assignment, see
the Pin Conversion Tables on page 18 of
the ON Semiconductor MECL Data
Book (DL122/D).
http://
ORDERING INFORMATION
MARKING
DIAGRAMS
= Assembly Location = Wafer Lot = Year = Work Week
CDIP–16
L SUFFIX
CASE 620
PDIP–16
P SUFFIX
CASE 648
PLCC–20
FN SUFFIX
CASE 775

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