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MC10EP35DR2ONN/a12000avai3.3V / 5V ECL JK Flip Flop


MC10EP35DR2 ,3.3V / 5V ECL JK Flip Flop3MC10EP35, MC100EP35100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 9.)CC EE–40°C 25°C 85°C ..
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MC10EP35DR2
3.3V / 5V ECL JK Flip Flop
MC10EP35, MC100EP35
3.3V / 5V�ECL JK Flip-Flop
The MC10/100EP35 is a higher speed/low voltage version of the
EL35 JK flip–flop. The J/K data enters the master portion of the
flip–flop when the clock is LOW and is transferred to the slave, and
thus the outputs, upon a positive transition of the clock. The reset pin is
asynchronous and is activated with a logic HIGH.
The 100 Series contains temperature compensation. 410 ps Propagation Delay Maximum Frequency > 3 GHz Typical PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V NECL Mode Operating Range: VCC = 0 V
with VEE = –3.0 V to –5.5 V Open Input Default State Q Output Will Default LOW with Inputs Open or at VEE
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