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MC10ELT22DR2ON SemiconductorN/a9190avai5V Dual TTL to Differential PECL Translator


MC10ELT22DR2 ,5V Dual TTL to Differential PECL TranslatorLogic Diagram and Pinout AssignmentORDERING INFORMATIONDevice Package Shipping**PIN DESCRIPTIONMC10 ..
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MC10ELT22DR2
5V Dual TTL to Differential PECL Translator
MC10ELT22, MC100EL T22
5V�Dual TTL to Differential
PECL Translator
The MC10ELT/100ELT22 is a dual TTL to differential PECL
translator. Because PECL (Positive ECL) levels are used only +5 V
and ground are required. The small outline 8-lead package and the low
skew, dual gate design of the ELT22 makes it ideal for applications
which require the translation of a clock and a data signal. 1.2 ns Typical Propagation Delay < 300 ps Typical Output to Output Skew PNP TTL Inputs for Minimal Loading Flow Through Pinouts Operating Range: VCC = 4.75 V to 5.25 V with GND = 0 V No Internal Input Pulldown Resistors
GND
VCC
Figure 1. Logic Diagram and Pinout Assignment
Q1
PIN DESCRIPTION

* Output state undetermined when inputs are open.
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