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MC10E1651L
Dual ECL output comparator with latch
SEMICONDUCTOR TECHNICAL DATA --
The MC10E1651 is functionally and pin-for-pin compatible with the
MC1651 in the MECL III family, but is fabricated using Motorola’s
advanced MOSAIC III process. The MC10E1651 incorporates a fixed
level of input hysteresis as well as output compatibility with 10KH logic
devices. In addition, a latch is available allowing a sample and hold
function to be performed. The device is available in both a 16-pin DIP and
a 20-pin surface mount package.
The latch enable (LENa and LENb) input pins operate from standard
ECL 10KH logic levels. When the latch enable is at a logic high level the
MC10E1651 acts as a comparator, hence Q will be at a logic high level if
V1 > V2 (V1 is more positive than V2). Q is the complement of Q. When
the latch enable input goes to a low logic level, the outputs are latched in
their present state providing the latch enable setup and hold time
constraints are met. Typ. 3.0 dB Bandwidth > 1.0 GHz Typ. V to Q Propagation Delay of 775 ps Typ. Output Rise/Fall of 350 ps Common Mode Range –2.0 V to +3.0 V Individual Latch Enables Differential Outputs 28mV Input Hysteresis
LENa
V2a
V1a
LENb
V2b
V1b
LOGIC DIAGRAMVEE = –5.2 V
VCC = +5.0 V
FUNCTION TABLE
