MC10175FN ,Quint LatchLOGIC DIAGRAMD0 10 D Q 14 Q0CRDIPPIN ASSIGNMENTD1 12 D Q 15 Q1CRV 1 16 VCC1 CC2Q2 Q12 15D2 13 D Q 2 ..
MC10175L ,Quint LatchLOGIC DIAGRAMD0 10 D Q 14 Q0CRDIPPIN ASSIGNMENTD1 12 D Q 15 Q1CRV 1 16 VCC1 CC2Q2 Q12 15D2 13 D Q 2 ..
MC10175P ,Quint LatchELECTRICAL CHARACTERISTICSTest LimitsPi Pin–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10176L ,Hex D Master/Slave Flip-FlopLOGIC DIAGRAMFN SUFFIXPLCCCASE 775–02D0 5 2 Q0DIPD1 6 3 Q1PIN ASSIGNMENTV V1 16CC1 CC2D2 7 4 Q2Q0 Q ..
MC10176P ,Hex D Master/Slave Flip-FlopELECTRICAL CHARACTERISTICSTest LimitsPi Pin–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10178L ,Binary CounterLOGIC DIAGRAMCASE 648–08FN SUFFIXS0 Q0 S1 Q1 S2 Q2 S3 Q3PLCC11 15 7 13 6 4 5 2CASE 775–02S S S SD1 ..
MC3359P ,HIGH GAIN LOW POWER FM IFOrder this document by MC3359/D ** * ** **...includes oscillator, mixer, limiting amplifier, AFC, ..
MC3361 ,Low Power Narrowband FM IFMaximum Ratings are those values beyond which damage to the device may occur.Functional operation s ..
MC3361BD ,LOW POWER NARROWBAND FM IFOrder this document by MC3361B/D* ** * ** **The MC3361B includes an Oscillator, Mixer, Limiting Am ..
MC3361BP ,Low voltage/power narrow band FM IF. Operating voltage: 2.5-7.0V. Operating current: 4.0mA(squelch off V12=2V), 6.0mA(squelch on V12=GND).Maximum Ratings are those values beyond which damage to the device may occur.Functional operation s ..
MC3361BPG-S16-R , LOW VOLTAGE/POWER NARROW BAND FM IF
MC3361BPL-S16-R , LOW VOLTAGE/POWER NARROW BAND FM IF
MC10175FN -MC10175L-MC10175P
Quint Latch
SEMICONDUCTOR TECHNICAL DATA-
The MC10175 is a high speed, low power quint latch. It features five D type
latches with common reset and a common two–input clock. Data is transferred
on the negative edge of the clock and latched on the positive edge. The two
clock inputs are “OR”ed together.
Any change on the data input will be reflected at the outputs while the clock
is low. The outputs are latched on the positive transition of the clock. While the
clock is in the high state, a change in the information present at the data inputs
will not affect the output information. The reset input is enabled only when the
clock is in the high state. = 400 mW typ/pkg (No Load)
tpd = 2.5 ns typ (Data to Output)
tr, tf = 2.0 ns typ (20%–80%)
LOGIC DIAGRAMVCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8 14
RESET 2
TRUTH TABLE
DIP
PIN ASSIGNMENTVCC1
VEE
VCC2
RESET
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
