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MC10111LMOTN/a548avaiDual 3-Input/3-Output NOR Gate
MC10111PMOTON/a157avaiDual 3-Input/3-Output NOR Gate
MC10111PMOTN/a101avaiDual 3-Input/3-Output NOR Gate


MC10111L ,Dual 3-Input/3-Output NOR GateLOGIC DIAGRAM DIPPIN ASSIGNMENT23546 V V1 16CC1 CC27A V2 1512 OUT CC113B9 A 3 14OUTOUT141011A 4 13 ..
MC10111P ,Dual 3-Input/3-Output NOR GateELECTRICAL CHARACTERISTICSTest LimitsPi Pin–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10111P ,Dual 3-Input/3-Output NOR GateLOGIC DIAGRAM DIPPIN ASSIGNMENT23546 V V1 16CC1 CC27A V2 1512 OUT CC113B9 A 3 14OUTOUT141011A 4 13 ..
MC10113FN ,Quad Exclusive OR GateELECTRICAL CHARACTERISTICSTest LimitsPin Pi–30°C +25°C +85°CUnder UnderCharacteristic Symbol Test U ..
MC10113FN ,Quad Exclusive OR Gate**SEMICONDUCTOR TECHNICAL DATA* ** **The MC10113 is a quad Exclusive OR gate, with an enable commo ..
MC10113L ,Quad Exclusive OR GateLOGIC DIAGRAMFN SUFFIXPLCCE 9CASE 775–02425DIPTRUTH TABLEPIN ASSIGNMENT6IN E OUTPUT37 V 1 16 VL L L ..
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MC33272ADR2 ,Single Supply, High Slew Rate, Low Input Offset Voltage, Dual Op AmpMAXIMUM RATINGSRating Symbol Value UnitSupply Voltage V to V +36 VCC EEInput Differential Voltage R ..
MC33272ADR2G , Single Supply, High Slew Rate, Low Input Offset Voltage Operational Amplifiers
MC33272ADR2G , Single Supply, High Slew Rate, Low Input Offset Voltage Operational Amplifiers
MC33272AP ,HIGH PERFORMANCE OPERATIONAL AMPLIFIERSOrder this document by MC33272A/D* " * * * ! *HIGH PERFORMANCE**! * * ** **OPERATIONAL* ** *AMPLI ..


MC10111L-MC10111P
Dual 3-Input/3-Output NOR Gate
SEMICONDUCTOR TECHNICAL DATA -
The MC10111 is designed to drive up to three transmission lines simul–
taneously. The multiple outputs of this device also allow the wire “OR”–ing of
several levels of gating for minimization of gate and package count.
The ability to control three parallel lines from a single point makes the
MC10111 particularly useful in clock distribution applications where minimum
clock skew is desired. Three VCC pins are provided and each one should be
used. = 80 mW typ/gate (No Load)
tpd = 2.4 ns typ (All Outputs Loaded)
tr, tf = 2.2 ns typ (20%–80%)
LOGIC DIAGRAM

VCC1 = PIN 1,15
VCC2 = PIN 16
VEE = PIN 8109 136 3
DIP
PIN ASSIGNMENT

VCC1
AOUT
AOUT
AOUT
AIN
AIN
AIN
VEE
VCC2
VCC1
BOUT
BOUT
BOUT
BIN
BIN
BIN
Pin assignment is for Dual–in–Line Package.
For PLCC pin assignment, see the Pin Conversion
Tables on page 6–11 of the Motorola MECL Data
Book (DL122/D).
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