MC100EL34D ,5V ECL Divide by 2, Divide by 4, Divide by 8 Clock Generation Chiphttp://onsemi.com3MC10EL34, MC100EL34Table 5. 10EL SERIES PECL DC CHARACTERISTICS V = 5.0 V; V = 0 ..
MC100EL34DG , 5V ECL ÷2, ÷4, ÷8 Clock Generation Chip
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MC33063ADRE4 ,1.5-A Peak Boost/Buck/Inverting Switching Regulator 8-SOIC -40 to 85Maximum Ratings.. 411 Layout.... 177.2 ESD Ratings........ 411.1 Layout Guidelines.... 177.3 Recomm ..
MC33063ADRG4 ,1.5-A Peak Boost/Buck/Inverting Switching Regulator 8-SOIC -40 to 85Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, and functio ..
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MC33063AP ,Product informationFeatures Description• Operation from 3.0 to 40V input The MC34063A/MC33063A is a monolithic regulat ..
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MC100EL34D
5V ECL Divide by 2, Divide by 4, Divide by 8 Clock Generation Chip
MC10EL34, MC100EL34
5V�ECL ÷2, ÷4, ÷8 Clock
Generation Chip
The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The VBB pin, an internally
generated voltage supply, is available to this device only. For
single-ended input conditions, the unused differential input is
connected to VBB as a switching reference voltage. VBB may also
rebias AC coupled inputs. When used, decouple VBB and VCC via a
0.01 �F capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, VBB should be left open.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. An internal runt pulse
could lead to losing synchronization between the internal divider
stages. The internal enable flip−flop is clocked on the falling edge of
the input clock, therefore, all associated specification limits are
referenced to the negative edge of the clock input.
Upon startup, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple EL34s in a system.
The 100 Series contains temperature compensation. 50 ps Output-to-Output Skew Synchronous Enable/Disable Master Reset for Synchronization PECL Mode Operating Range:
VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range:
VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input 75 k� Pulldown Resistors on CLK(s), EN, and MR Pb−Free Packages are Available
